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PDF ADN4666 Data sheet ( Hoja de datos )

Número de pieza ADN4666
Descripción Quad CMOS Differential Line Receiver
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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FEATURES
±8 kV ESD IEC 61000-4-2 contact discharge on receiver input pins
400 Mbps (200 MHz) switching rates
100 ps channel-to-channel skew (typical)
100 ps differential skew (typical)
3.3 ns propagation delay (maximum)
3.3 V power supply
High impedance outputs on power-down
Low power design (10 mW quiescent typical)
Interoperable with existing 5 V LVDS drivers
Accepts small swing (350 mV typical) differential
input signal levels
Supports open, short, and terminated input fail-safe
Conforms to TIA/EIA-644 LVDS standard
Industrial operating temperature range of −40°C to +85°C
Available in surface-mount SOIC package and low profile
TSSOP package
APPLICATIONS
Point-to-point data transmission
Multidrop buses
Clock distribution networks
Backplane receivers
GENERAL DESCRIPTION
The ADN4666 is a quad-channel, CMOS low voltage differential
signaling (LVDS) line receiver offering data rates of over 400 Mbps
(200 MHz) and ultralow power consumption.
The device accepts low voltage (350 mV typical) differential
input signals and converts them to a single-ended, 3 V TTL/CMOS
logic level.
The ADN4666 also offers active high and active low enable/disable
inputs (EN and EN) that control all four receivers. These inputs
3 V, LVDS, Quad CMOS
Differential Line Receiver
ADN4666
FUNCTIONAL BLOCK DIAGRAM
RIN1–
RIN1+
ADN4666
R1 R4
VCC
RIN4–
RIN4+
ROUT1
EN
ROUT4
EN
ROUT2
RIN2+
RIN2–
GND
R2 R3
Figure 1.
ROUT3
RIN3+
RIN3–
disable the receivers and switch the outputs to a high impedance
state. Consequently, the outputs of one or more ADN4666
devices can be multiplexed together to reduce the quiescent
power consumption to 10 mW typical.
The ADN4666 and its companion driver, the ADN4665, offer
a new solution to high speed, point-to-point data transmission
and offer a low power alternative to emitter-coupled logic (ECL)
or positive emitter-coupled logic (PECL).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.

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ADN4666 pdf
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RINx–
RINx+
0V (DIFFERENTIAL) VID = 300mV p-p
1.2V
tPLHD
tPHLD
80% 80%
1.3V
1.1V
VOH
ROUTx
1.5V
1.5V
20%
20%
tTLH
tTHL
VOL
Figure 3. Receiver Propagation Delay and Transition Time Waveforms
ADN4666
VCC
S1
SIGNAL
GENERATOR
RINx+
RINx–
EN
50
EN
GND
RL
ROUTx
CL
NOTES
1. CL INCLUDES LOAD AND TEST JIG CAPACITANCE.
2. S1 CONNECTED TO VCC FOR tPZL AND tPLZ MEASUREMENTS.
3. S1 CONNECTED TO GND FOR tPZH AND tPHZ MEASUREMENTS.
Figure 4. Test Circuit for Receiver Enable/Disable Delay
EN WITH EN = GND
OR OPEN CIRCUIT
1.5V
1.5V
EN WITH EN = VCC
1.5V
ROUTx WITH VID = +100mV
tPHZ
0.5V
1.5V
tPZH
50%
ROUTx WITH VID = –100mV
tPLZ
0.5V
tPZL
Figure 5. Receiver Enable/Disable Delay Waveforms
50%
3V
0V
3V
0V
VOH
GND
VCC
VOL
Rev. 0 | Page 5 of 12

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NOTES
ADN4666
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