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PDF 74AUP1T57 Data sheet ( Hoja de datos )
| Número de pieza | 74AUP1T57 | |
| Descripción | Low-power Configurable Gate | |
| Fabricantes | NXP Semiconductors | |
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74AUP1T57
Low-power configurable gate with voltage-level translator
Rev. 01 — 3 January 2008
Product data sheet
1. General description
The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected
to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 2.3 V to 3.6 V.
The 74AUP1T57 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the
entire VCC range.
2. Features
s Wide supply voltage range from 2.3 V to 3.6 V
s High noise immunity
s ESD protection:
x HBM JESD22-A114E Class 3A exceeds 5000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101C exceeds 1000 V
s Low static power consumption; ICC = 1.5 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C
1 page  
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74AUP1T57
Low-power configurable gate with voltage-level translator
VCC
Fig 11. Buffer
B1
6
BY
25
3 4Y
001aab590
8. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC
IIK
VI
IOK
VO
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
quiescent supply current
ground current
storage temperature
total power dissipation
VI < 0 V
VO > VCC or VO < 0 V
Active mode and Power-down mode
VO = 0 V to VCC
Tamb = −40 °C to +125 °C
−0.5
−50
[1] −0.5
-
[1] −0.5
-
-
−50
−65
[2] -
+4.6
-
+4.6
±50
+4.6
±20
50
-
+150
250
V
mA
V
mA
V
mA
mA
mA
°C
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SC-88 package: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
VCC
VI
VO
Tamb
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
Conditions
Active mode
Power-down mode; VCC = 0 V
Min Max Unit
2.3 3.6 V
0 3.6 V
0
VCC
V
0 3.6 V
−40 +125 °C
74AUP1T57_1
Product data sheet
Rev. 01 — 3 January 2008
© NXP B.V. 2008. All rights reserved.
5 of 17
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74AUP1T57
Low-power configurable gate with voltage-level translator
VCC
VEXT
G VI
DUT
VO
5 kΩ
RT CL RL
001aac521
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 13. Load circuitry for switching times
Table 11. Test data
Supply voltage
Load
VCC
2.3 V to 3.6 V
CL
5 pF, 10 pF, 15 pF and 30 pF
RL[1]
5 kΩ or 1 MΩ
VEXT
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2 × VCC
[1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.
74AUP1T57_1
Product data sheet
Rev. 01 — 3 January 2008
© NXP B.V. 2008. All rights reserved.
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