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PDF ADCLK854 Data sheet ( Hoja de datos )
| Número de pieza | ADCLK854 | |
| Descripción | Low Power Clock Fanout Buffer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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1.8 V, 12-LVDS/24-CMOS Output,
Low Power Clock Fanout Buffer
ADCLK854
FEATURES
2 selectable differential inputs
Selectable LVDS/CMOS outputs
Up to 12 LVDS (1.2 GHz) or 24 CMOS (250 MHz) outputs
<12 mW per channel (100 MHz operation)
54 fs rms integrated jitter (12 kHz to 20 MHz)
100 fs rms additive broadband jitter
2.0 ns propagation delay (LVDS)
135 ps output rise/fall (LVDS)
70 ps output-to-output skew (LVDS)
Sleep mode
Pin programmable control
1.8 V power supply
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
GENERAL DESCRIPTION
The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout
buffer optimized for low jitter and low power operation. Possible
configurations range from 12 LVDS to 24 CMOS outputs,
including combinations of LVDS and CMOS outputs. Three
control lines are used to determine whether fixed blocks of
outputs (three banks of four) are LVDS or CMOS outputs.
The ADCLK854 offers two selectable inputs and a sleep mode
feature. The IN_SEL pin state determines which input is fanned
out to all the outputs. The SLEEP pin enables a sleep mode to
power down the device.
The inputs accept various types of single-ended and differential
logic levels including LVPECL, LVDS, HSTL, CML, and CMOS.
Table 8 provides interface options for each type of connection.
This device is available in a 48-pin LFCSP package. It is specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
ADCLK854
VREF
VS/2
LVDS/
CMOS
OUT0 (OUT0A)
OUT0 (OUT0B)
CLK0
CLK0
CLK1
CLK1
IN_SEL
CTRL_A
OUT1 (OUT1A)
OUT1 (OUT1B)
OUT2 (OUT2A)
OUT2 (OUT2B)
OUT3 (OUT3A)
OUT3 (OUT3B)
CTRL_B
LVDS/
CMOS
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
CTRL_C
SLEEP
LVDS/
CMOS
OUT8 (OUT8A)
OUT8 (OUT8B)
OUT9 (OUT9A)
OUT9 (OUT9B)
OUT10 (OUT10A)
OUT10 (OUT10B)
OUT11 (OUT11A)
OUT11 (OUT11B)
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalog Devicesforitsuse,norforanyinfringementsofpatentsorother
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
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CLOCK CHARACTERISTICS
Table 3. Clock Output Phase Noise
Parameter
CLOCK-TO-LVDS ABSOLUTE PHASE NOISE
1000 MHz
CLOCK-TO-CMOS ABSOLUTE PHASE NOISE
200 MHz
ADCLK854
Min Typ
Max Unit
−90
−108
−117
−126
−135
−141
−146
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−101
−119
−127
−138
−147
−153
−156
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Conditions
Input slew rate > 1 V/ns
@ 10 Hz offset
@ 100 Hz offset
@ 1 kHz offset
@ 10 kHz offset
@ 100 kHz offset
@ 1 MHz offset
@ 10 MHz offset
Input slew rate > 1 V/ns
@ 10 Hz offset
@ 100 Hz offset
@ 1 kHz offset
@ 10 kHz offset
@ 100 kHz offset
@ 1 MHz offset
@ 10 MHz offset
LOGIC AND POWER CHARACTERISTICS
Table 4. Control Pin Characteristics
Parameter
Symbol Min
Typ Max Unit Conditions
CONTROL PINS (IN_SEL, CTRL_x, SLEEP)1
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
VIH VS − 0.4
V
VIL 0.4 V
IIH 5 8 20 μA
IIL −5
+5 μA
2 pF
POWER
Supply Voltage Requirement
LVDS Outputs
VS
1.71 1.8 1.89 V
VS = 1.8 V ± 5%
Full operation
LVDS @ 100 MHz
LVDS @ 1200 MHz
CMOS Outputs
84 100 mA
175 215 mA
All outputs enabled as LVDS and loaded, RL = 100 Ω
All outputs enabled as LVDS and loaded, RL = 100 Ω
Full operation
CMOS @ 100 MHz
CMOS @ 250 MHz
SLEEP
115 140
265 325
3
mA
mA
mA
All outputs enabled as CMOS and loaded, CL = 10 pF
All outputs enabled as CMOS and loaded, CL = 10 pF
SLEEP pin pulled high; does not include power dissipated
in the external resistors
Power Supply Rejection 2
LVDS
CMOS
PSR t PD
PSR tPD
0.9 ps/mV
1.2 ps/mV
1 These pins each have a 200 kΩ internal pull-down resistor.
2 Change in tPD per change in VS.
Rev. 0 | Page 5 of 16
5 Page 
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ADCLK854
1
CH1 300mV
1.25ns/DIV
CH1 954mV
Figure 15. CMOS Output Waveform @ 200 MHz (10 pF Load)
1.9
1.8
25°C
1.7
1.6
85°C
1.5
1.4
1.3
1.2
1.1
50
100 150 200
FREQUENCY (MHz)
250
Figure 16. CMOS Output Swing vs. Frequency by Temperature (10 pF Load)
2.0
1.9
1.8 CL = 5pF
1.7
CL = 10pF
1.6
1.5 CL = 20pF
1.4
1.3
1.2
1.1
1.0
0
50 100 150 200
FREQUENCY (MHz)
250
Figure 17. CMOS Output Swing vs. Frequency by Capacitive Load
1
CH1 300mV
5.0ns/DIV
CH1 954mV
Figure 18. CMOS Output Waveform @ 50 MHz (10 pF Load)
1.8
RLOAD = 750Ω
RLOAD = 1kΩ
1.7
1.6
RLOAD = 500Ω
RLOAD = 300Ω
1.5
1.4
0
50 100 150 200
FREQUENCY (MHz)
250
Figure 19. CMOS Output Swing vs. Frequency by Resistive Load
Rev. 0 | Page 11 of 16
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