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PDF MAX3882 Data sheet ( Hoja de datos )
| Número de pieza | MAX3882 | |
| Descripción | 2.488Gbps/2.67Gbps 1:4 Demultiplexer | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-2718; Rev 0; 1/03
www.DataSheet4U.com
2.488Gbps/2.67Gbps 1:4 Demultiplexer with
Clock and Data Recovery and Limiting Amplifier
General Description
The MAX3882 is a deserializer combined with clock
and data recovery and limiting amplifier ideal for con-
verting 2.488Gbps/2.67Gbps serial data to 4-bit-wide,
622Mbps/667Mbps parallel data for SDH/SONET appli-
cations. The device accepts serial NRZ input data as
low as 10mVP-P of 2.488Gbps/2.67Gbps and generates
four parallel LVDS data outputs at 622Mbps/667Mbps.
Included is an additional high-speed serial data input
for system loopback diagnostic testing. For data acqui-
sition, the MAX3882 does not require an external refer-
ence clock. However, if needed, the loopback input
can be connected to an external reference clock of
155MHz/167MHz or 622MHz/667MHz to maintain a
valid clock output in the absence of input data transi-
tions. Additionally, a TTL-compatible loss-of-lock output
is provided. The device provides a vertical threshold
adjustment to compensate for optical noise generated
by EDFAs in WDM transmission systems. The MAX3882
operates from a single +3.3V supply and consumes
610mW.
The MAX3882’s jitter performance exceeds all SDH/
SONET specifications. The device is available in a 6mm
✕ 6mm 36-pin QFN package.
Applications
SDH/SONET Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
SDH/SONET Test Equipment
DWDM Transmission Systems
Features
o No Reference Clock Required for Data Acquisition
o Input Data Rates: 2.488Gbps or 2.67Gbps
o Fully Integrated Clock and Data Recovery with
Limiting Amplifier and 1:4 Demultiplexer
o Parallel Output Rate: 622Mbps/667Mbps
o Differential Input Range: 10mVP-P to 1.6VP-P with-
out Threshold Adjust
o Differential Input Range: 50mVP-P to 600mVP-P
with Threshold Adjust
o 0.65UI High-Frequency Jitter Tolerance
o Loss-of-Lock (LOL) Indicator
o Wide Input Threshold Adjust Range: ±170mV
o Maintain Valid Clock Output in Absence of Data
Transitions
o System Loopback Input Available for System
Diagnostic Testing
o Operating Temperature Range -40°C to +85°C
o Low Power Dissipation: 610mW at +3.3V
Ordering Information
PART
MAX3882EGX
TEMP RANGE
-40oC to +85oC
PIN-
PACKAGE
36 QFN
PKG
CODE
G3666-1
Pin Configuration
TOP VIEW
GND
VCC
SDI+
SDI-
VCC
SLBI+
SLBI-
SIS
LOL
1
2
3
4
5
6
7
8
9
MAX3882
27 PD3+
26 PD3-
25 PD2+
24 PD2-
23 GND
22 PD1+
21 PD1-
20 PD0+
19 PD0-
QFN
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with
Clock and Data Recovery and Limiting Amplifier
(TA = +25°C, unless otherwise noted.)
RECOVERED CLOCK AND DATA
(INPUT = 2.488Gbps, 223 - 1
PATTERN, VIN = 10mVP-P)
200mV/div
500ps/div
JITTER TOLERANCE vs. INPUT AMPLITUDE
(2.48832Gbps, 223 - 1 PATTERN, WITH
ADDITIONAL 0.15UI DETERMINISTIC JITTER)
0.6
0.5
JITTER FREQUENCY = 10MHz
0.4
0.3
0.2
0.1
0
1 10 100 1000 10,000
INPUT AMPLITUDE (mVP-P)
Typical Operating Characteristics
SUPPLY CURRENT vs. TEMPERATURE
260
250
240
230
220
210
200
190
180
170
160
-50 -25
0
25 50 75 100
TEMPERATURE (°C)
JITTER TOLERANCE
(2.48832Gbps, 223 - 1 PATTERN,
VIN = 16mVP-P WITH ADDITIONAL
0.15UI DETERMINISTIC JITTER)
100
10
1
BELLCORE
MASK
0.1
10
100 1k
JITTER FREQUENCY (Hz)
10k
5
0
-5
-10
-15
-20
-25
-30
-35
-40
1
JITTER TRANSFER
BELLCORE
MASK
10 100 1000
JITTER FREQUENCY (kHz)
10,000
PARALLEL CLOCK OUTPUT JITTER
fCLK = 622.08MHz
TOTAL WIDEBAND
RMS JITTER = 2.720ps
PEAK-TO-PEAK
JITTER = 20.80ps
20ps/div
BIT-ERROR RATE vs. INPUT AMPLITUDE
1.00E-04
1.00E-05
1.00E-06
1.00E-07
1.00E-08
1.00E-09
1.00E-10
1.00E-11
1
234
INPUT VOLTAGE (mVP-P)
5
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
-40
PULLIN RANGE
(RATESET = 0)
-15 10 35 60
AMBIENT TEMPERATURE (°C)
85
_______________________________________________________________________________________ 5
5 Page 
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with
Clock and Data Recovery and Limiting Amplifier
+3.3V
0.068µF
-3.3V
155MHz
CLOCK
SIS RATESET FIL VCC LREF
LOL
PD3+
SLBI+
SLBI-
TIA OUTPUT
AGC
MAX3861
0.1µF
0.1µF
R1
SDI+
SDI-
VCTRL
VREF
R2
R1 + R2 ≥ 50kΩ
MAX3882
PD3-
PD2+
PD2-
PD1+
PD1-
PD0+
PD0-
FREFSET CAZ+ CAZ-
PCLK+
PCLK-
+3.3V
0.1µF
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω.
Figure 8. Connecting the MAX3882 with Threshold Adjust and Clock Holdover Enabled
100Ω*
VCC
100Ω*
OVERHEAD
100Ω* TERMINATION
100Ω*
100Ω*
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MAX3882.PDF ] | |
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