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PDF ADP3634 Data sheet ( Hoja de datos )
| Número de pieza | ADP3634 | |
| Descripción | (ADP3624 / ADP3634) 4A MOSFET Driver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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High Speed, Dual, 4 A MOSFET Driver
with Thermal Protection
ADP3624/ADP3634
FEATURES
GENERAL DESCRIPTION
Industry-standard-compatible pinout
High current drive capability
Precise threshold shutdown comparator
UVLO with hysteresis
Overtemperature warning signal
Overtemperature shutdown
3.3 V-compatible inputs
10 ns typical rise time and fall time @ 2.2 nF load
Matched propagation delays between channels
Fast propagation delay
9.5 V to 18 V supply voltage (ADP3634)
4.5 V to 18 V supply voltage (ADP3624)
Parallelable dual outputs
Rated from −40°C to 85°C ambient temperature
Thermally enhanced packages, 8-lead SOIC_N_EP and
8-lead MINI_SO_EP
APPLICATIONS
AC-to-dc switch mode power supplies
DC-to-dc power supplies
Synchronous rectification
Motor drives
The ADP3624/ADP3634 are high current drive, dual high
speed drivers, capable of driving two independent N-channel
power MOSFETs. The part uses the industry-standard footprint
but adds high speed switching performance and improved
system reliability.
The part has an internal temperature sensor and provides two
levels of overtemperature protection, an overtemperature
warning and an overtemperature shutdown at extreme junction
temperatures.
The SD function, generated from a precise internal comparator,
provides fast system enable or shutdown. This feature allows
redundant overvoltage protection, complementing the
protection inside the main controller device, or provides safe
system shutdown in the event of an overtemperature warning.
Wide input voltage range allows the driver to be compatible
with both analog and digital PWM controllers.
Digital power controllers are supplied from a low voltage
supply, and the driver is supplied from a higher voltage supply.
The ADP3624/ADP3634 add UVLO and hysteresis functions,
allowing safe startup and shutdown of the higher voltage supply
when used with low voltage digital controllers.
The device family is available in thermally enhanced SOIC_N_EP
and MINI_SO_EP packaging to maximize high frequency and
current switching in a small printed circuit board (PCB) area.
FUNCTIONAL BLOCK DIAGRAM
VDD ADP3624/ADP3634
SD 1
INA 2
VEN
NONINVERTING
OVERTEMPERATURE
PROTECTION
VDD
8 OTW
7 OUTA
PGND 3
INB 4
INVERTING
NONINVERTING
UVLO
6 VDD
5 OUTB
INVERTING
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
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ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VDD
OUTA, OUTB
DC
<200 ns
INA, INB, SD
ESD
Human Body Model (HBM)
Field Induced Charged Device
Model (FICDM), SOIC_N_EP
Field Induced Charged Device
Model (FICDM), MINI_SO_EP
θJA, SOIC_N_EP1
JEDEC 4-Layer Board
θJA, MINI_SO_EP1
JEDEC 4-Layer Board
Junction Temperature Range
Storage Temperature Range
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.3 V to +20 V
−0.3 V to VDD + 0.3 V
−2 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
3.5 kV
1.5 kV
1.0 kV
59°C/W
43°C/W
−40°C to +150°C
−65°C to +150°C
300°C
215°C
260°C
1 θJA is measured per JEDEC standards JESD51-2, JESD51-5, and JESD51-7 as
appropriate with the exposed pad soldered to the PCB.
ADP3624/ADP3634
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 16
5 Page 
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VDD
3.3V
OTW
ADP3624/
ADP3634
PGND
VDD
OTW
FLAGIN
ADP1043A
ADP3624/ADP3634
• Place the VDD bypass capacitor as close as possible to the
VDD and PGND pins.
• Use vias to other layers, when possible, to maximize
thermal conduction away from the IC.
Figure 21 shows an example of the typical layout based on the
preceding guidelines.
ADP3624/
ADP3634
PGND
Figure 20. OTW Signaling Scheme Example
The OTW open-drain configuration allows connection of
multiple devices to the same warning bus in a wire-OR’ed
configuration, as shown in Figure 20.
The overtemperature shutdown turns off the device to protect it
in the event that the die temperature exceeds the absolute
maximum limit in Table 2.
SUPPLY CAPACITOR SELECTION
For the supply input (VDD) of the ADP3624/ADP3634, a local
bypass capacitor is recommended to reduce the noise and to
supply some of the peak currents that are drawn.
An improper decoupling can dramatically increase the rise
times, cause excessive resonance on the OUTA and OUTB pins,
and, in some extreme cases, even damage the device, due to
inductive overvoltage on the VDD or OUTA/OUTB pins.
The minimum capacitance required is determined by the size
of the gate capacitances being driven, but as a general rule, a
4.7 µF, low ESR capacitor should be used. Multilayer ceramic
chip (MLCC) capacitors provide the best combination of low
ESR and small size. Use a smaller ceramic capacitor (100 nF)
with a better high frequency characteristic in parallel to the
main capacitor to further reduce noise.
Keep the ceramic capacitor as close as possible to the ADP3624/
ADP3634, and minimize the length of the traces going from the
capacitor to the power pins of the device.
PCB LAYOUT CONSIDERATIONS
Use the following general guidelines when designing printed
circuit boards (PCBs):
• Trace out the high current paths and use short, wide
(>40 mil) traces to make these connections.
• Minimize trace inductance between the OUTA and OUTB
outputs and MOSFET gates.
• Connect the PGND pin of the ADP3624/ADP3634 as
closely as possible to the source of the MOSFETs.
Figure 21. External Component Placement Example
Note that the exposed pad of the package is not directly
connected to any pin of the package, but it is electrically and
thermally connected to the die substrate, which is the ground of
the device.
PARALLEL OPERATION
The two driver channels present in the ADP3624/ADP3634 can
be combined to operate in parallel to increase drive capability
and minimize power dissipation in the driver.
In this configuration, INA and INB are connected together, and
OUTA and OUTB are connected together. The connection
scheme is shown in Figure 22.
Particular attention must be paid to the layout in this case to
optimize load sharing between the two drivers.
1 SD
OTW 8
ADP3624/ADP3634
INA
2
OUTA
A7
3 PGND
VDD 6
VDD
VDS
4 INB
B OUTB 5
Figure 22. Parallel Operation
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADP3634.PDF ] | |
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