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PDF SA303 Data sheet ( Hoja de datos )
| Número de pieza | SA303 | |
| Descripción | 3-Phase Switching Amplifier IC | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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P r o d u c t IInnnnoovvaa t i o n FFr roomm
SAS3A03033
3 Phase Switching Amplifier
FEATURES
♦ Low Cost 3 Phase Intelligent Switching
Amplifier
♦ Directly Connects to Most Embedded Micro-
controllers and Digital Signal Controllers
♦ Integrated Gate Driver Logic with Dead-Time
Generation and Shoot-through Prevention
♦ Wide Power Supply Range (8.5V To 60V)
♦ Over 10A Peak Output Current per Phase
♦ 3A Continuous Output Current per Phase
♦ Independent Current Sensing for each Output
♦ User Programmable Cycle-by-cycle Current
Limit Protection
♦ Over-Current and Over-Temperature Warning
Signals
APPLICATIONS
♦ 3 phase brushless DC motors
♦ Multiple DC brush motors
♦ 3 independent solenoid actuators
DESCRIPTION
The SA303 is a fully integrated switching amplifier
designed primarily to drive three-phase Brushless
DC (BLDC) motors. Three independent half bridges
provide over 10 amperes peak output current under
microcontroller or DSC control. Thermal and short cir-
cuit monitoring is provided, which generates fault sig-
nals for the microcontroller to take appropriate action.
A block diagram is provided in Figure 1.
Additionally, cycle-by-cycle current limit offers user
programmable hardware protection independent of the
microcontroller. Output current is measured using an
innovative low loss technique. The SA303 is built using
a multi-technology process allowing CMOS logic con-
trol and complementary DMOS output power devices
on the same IC. Use of P-channel high side FETs en-
ables 60V operation without bootstrap or charge pump
circuitry.
The Power Quad surface mount package balances ex-
cellent thermal performance with the advantages of a
low profile surface mount package.
SC
TEMP
ILIM/D IS 1
Ia
Ib
Ic
D IS 2
At
Ab
PWM
Signals
Bt
Bb
Ct
Cb
SGND
Figure 1. BLOCK Diagram
VDD
Vs (phase A)
VS +
Vs (phase B&C)
Fault
Logic
Ia'
Ib'
Ic'
VDD
VDD
VDD
Gate
Control
Phase A
Control
Logic
Phase B
Ia' Ib' Ic'
A Out A
B Out B
C Out C
Phase C
SA303 Switching Amplifier
P G N D (A & B )
GND
P G N D (C )
SA303U
http://www.cirrus.com
Copyrig( Ahtll©RiCghirtrsusRLeosgeircv,eIdn)c. 2009
MAY 2009
APEX − SA303UREVA
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Figure 3. External Connections
OUT C
NC
PGND C
PGND C
PGND C
HS
53
54
55
56
57
58
SA303
32 NC
31 VS A
30 VS A
29 VS A
28 NC
27 HS
HS 59
NC 60
Cb 61
NC 62
Ct 63
NC 64
26 HS
25 TEMP
24 NC
23 DIS2
22 NC
21 Ia
Table 1. Pin Descriptions
Pin #
Pin Name
Signal Type
29,30,31
51,52,53
VS (phase A)
OUT C
Power
Power Output
55,56,57
PGND (phase C) Power
3 SC
Logic Output
61 Cb
Logic Input
63 Ct
Logic Input
1 Ic
Analog Output
5 Ib
Analog Output
7 ILIM/DIS1 Logic Input/Output
Simplified Pin Description
High Voltage Supply (8.5-60V) supplies phase A only
Half Bridge C Power Output
High Current GND Return Path for Power Output C
Indication of a short of an output to supply, GND or another phase
Logic high commands C phase lower FET to turn on
Logic high commands C phase upper FET to turn on
Phase C current sense output
Phase B current sense output
As an output, logic high indicates cycle-by-cycle current limit, and
logic low indicates normal operation. As an input, logic high places
all outputs in a high impedance state and logic low disables the
cycle-by-cycle current limit function.
SA303U
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Product Innova tionFrom
SA303
out condition is in progress. The SA303 has two
VS connections: one for phase A, and another for
phases B & C. The supply voltages on these pins
need not be the same, but the UVLO will engage
if either is below the threshold. Hysteresis on the
UVLO circuit prevents oscillations with typical
power supply variations.
Figure 7. Start-up Voltage and
Current
NON-LIMITED MOTOR CURRENT
NON-LIMITED BACK EMF
2.4 CURRENT SENSE
External power shunt resistors are not required
with the SA303. Forward current in each top,
LIMITED BACK EMF
Pchannel output FET is measured and mirrored to
the respective current sense output pin, Ia, Ib and
Ic. By connecting a resistor between each cur-
rent sense pin and a reference, such as ground,
LIMITED MOTOR CURRENT
a voltage develops across the resistor that is pro-
portional to the output current for that phase. An
ADC can monitor the voltages on these resistors
for protection or for closed loop torque control
in some application configurations. The current
sense pins source current from the VDD supply.
Headroom required for the current sense circuit is
TIME
approximately .5V. The nominal scale factor for each proportional output current is shown in the typical performance
plot on page 4 of this datasheet.
2.5 CYCLE-BY-CYCLE CURRENT LIMIT
In applications where the current in the motor is not directly controlled, both the average current rating of the mo-
tor and the inrush current must be considered when selecting a proper amplifier. For example, a 1A continuous
motor might require a drive amplifier that can deliver well over 10A peak in order to survive the inrush condition at
startup.
Because the output current of each upper output FET is measured, the SA303 is able to provide a very robust cur-
rent limit scheme. This enables the SA303 to safely and easily drive virtually any brushless motor through a startup
inrush condition. With limited current, the starting torque and acceleration are also limited. The plot in Figure 7
shows starting current and back EMF with and without current limit enabled.
If the voltage of any of the three current sense pins exceeds the current limit threshold voltage (Vth), all outputs are
disabled. After all current sense pins fall below the Vth threshold voltage AND the offending phase’s top side input
goes low, the output stage will return to an active state on the rising edge of ANY top side input command signal (At,
Bt, or Ct). With most commutation schemes, the current limit will reset each pwm cycle. This scheme regulates the
peak current in each phase during each pwm cycle as illustrated in the timing diagram below. The ratio of average
to peak current depends on the inductance of the motor winding, the back EMF developed in the motor, and the
width of the pulse.
Figure 8 illustrates the current limit trigger and reset sequence. Current limit engages and ILIM/DIS1 goes high when
any current sense pin exceeds Vth. Notice that the moment at which the current sense signal exceeds the Vth
threshold is asynchronous with respect to the input PWM signal. The difference between the PWM period and the
motor winding L/R time constant will often result in an audible beat frequency sometimes called a sub-cycle oscil-
lation.
This oscillation can be seen on the ILIM/DIS1 pin waveform in Figure 8. Input signals commanding 0% or 100% duty
cycle may be incompatible with the current limit feature due to the absence of rising edges of At, Bt, and Ct except
when commutating phases. At high RPM, this may result in poor performance. At low RPM, the motor may stall if
the current limit trips and the motor current reaches zero without a commutation edge which will typically reset the
current limit latch.
SA303U
11
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet SA303.PDF ] | |
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