PDF WSE128K16-xxx Data sheet ( Hoja de datos )

Número de pieza	WSE128K16-xxx
Descripción	128Kx16 SRAM/EEPROM MODULE
Fabricantes	White Electronic Designs Corporation
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No Preview Available ! White Electronic Designs www.DataSheet4U.com WSE128K16-XXX PRELIMINARY* 128Kx16 SRAM/EEPROM MODULE FEATURES Access Times of 35ns (SRAM) and 150ns (EEPROM) Access Times of 45ns (SRAM) and 120ns (EEPROM) Access Times of 70ns (SRAM) and 300ns (EEPROM) Packaging • 66 pin, PGA Type, 1.075" square HIP, Hermetic Ceramic HIP (H1) (Package 400) Commercial, Industrial and Military Temperature Ranges TTL Compatible Inputs and Outputs Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Weight - 13 grams typical EEPROM MEMORY FEATURES • 68 lead, Hermetic CQFP (G2T), 22mm (0.880") square (Package 509). Designed to ﬁt JEDEC 68 lead 0.990" CQFJ footprint (FIGURE 2) 128Kx16 SRAM 128Kx16 EEPROM Organized as 128Kx16 of SRAM and 128Kx16 of EEPROM Memory with separate Data Buses Write Endurance 10,000 Cycles Data Retention at 25°C, 10 Years Low Power CMOS Operation Automatic Page Write Operation Page Write Cycle Time 10ms Max. Data Polling for End of Write Detection Both blocks of memory are User Conﬁgurable as 256Kx8 Hardware and Software Data Protection TTL Compatible Inputs and Outputs Low Power CMOS * This product is under development, is not qualiﬁed or characterized and is subject to change without notice. FIGURE 1 – WSE128K16-XH1X PIN CONFIGURATION Top View 1 12 23 34 45 56 SD8 SWE2# SD15 ED8 VCC ED15 SD9 SCS2# SD14 ED9 ECS2# ED14 SD10 GND SD13 ED10 EWE2# ED13 A13 SD11 SD12 A6 ED11 ED12 A14 A10 OE# A7 A3 A0 A15 A11 NC NC A4 A1 PIN DESCRIPTION ED0-15 SD0-15 A0-16 SWE#1-2 SCS#1-2 OE# VCC GND NC EWE#1-2 ECS#1-2 EEPROM Data Inputs/Outputs SRAM Data Inputs/Outputs Address Inputs SRAM Write Enable SRAM Chip Selects Output Enable Power Supply Ground Not Connected EEPROM Write Enable EEPROM Chip Select A16 A12 SWE#1 NC VCC SD7 SD0 SCS1# SD6 SD1 NC SD5 A8 A5 A9 EWE1# ED0 ECS1# ED1 GND A2 ED7 ED6 ED5 BLOCK DIAGRAM OE# A0-16 SWE1# SCS1# SWE2# SCS2# EWE1# ECS1# EWE2# ECS2# 128K x 8 SRAM 128K x 8 SRAM 128K x 8 EEPROM 128K x 8 EEPROM SD2 SD3 SD4 11 22 33 ED2 ED3 ED5 44 55 66 8 SD0-7 8 SD8-15 8 ED0-7 8 ED8-15 White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. March 2005 Rev. 3 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs www.DataSheet4U.com WSE128K16-XXX PRELIMINARY ADDRESS SRAM DATA I/O FIGURE 4 – SRAM READ CYCLES tRC tAA tOH PREVIOUS DATA VALID DATA VALID READ CYCLE 1, (SCS# = OE# = VIL, SWE# = VIH) ADDRESS tRC tAA SCS# SOE# SRAM DATA I/O tACS tCLZ tOE tOLZ HIGH IMPEDANCE tCHZ tOHZ DATA VALID READ CYCEL 2, (SWE# = VIH) FIGURE 5 – SRAM WRITE CYCLE SWE# CONTROLLED ADDRESS SCS# SWE# SRAM DATA I/O tWC tAW tCW tAH tAS tWP tWHZ tOW tDW tDH DATA VALID WRITE CYCLE 1, SWE# CONTROLLED FIGURE 6 – SRAM WRITE CYCEL SCS# CONTROLLED ADDRESS SCS# SWE# SRAM DATA I/O tWC tAW tAS tCW tAH tWP tDW tDH DATA VALID WRITE CYCLE 2, SCS# CONTROLLED White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. March 2005 Rev. 3 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page White Electronic Designs www.DataSheet4U.com WSE128K16-XXX PRELIMINARY FIGURE 12 – EEPROM SOFTWARE DATA PROTECTION ENABLE ALGORITHM(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE NOTES: 1. Data Format: ED7 - ED0 (Hex); Address Format: A16 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. March 2005 Rev. 3 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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