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PDF DS34RT5110 Data sheet ( Hoja de datos )
| Número de pieza | DS34RT5110 | |
| Descripción | HDMI Retimer | |
| Fabricantes | National Semiconductor Corporation | |
| Logotipo |  |
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DS34RT5110
PRELIMINARY
May 11, 2009
DVI, HDMI Retimer with Input Equalization and Output De-
Emphasis
General Description
The DS34RT5110 is a 10.2 Gbps (3 x 3.4 Gbps) high perfor-
mance re-clocking device that supports 3 Transition Mini-
mized Differential Signaling (TMDS®) data channels and a
single clock channel over DVI™ v1.0, and HDMI™ v1.3a data
rates up to 3.4 Gbps for each data channel. The device in-
corporates a configurable receive equalizer, a clock and data
recovery (CDR) circuit and a de-emphasis driver on each data
channel. The clock channel feeds a high-performance phase-
locked loop (PLL) that regenerates a low jitter output clock for
data recovery.
The DS34RT5110 equalizes and retimes greater than 25 me-
ters 28 AWG of HDMI cable for 1080p resolution with 12 bit
deep color depth (2.25 Gbps), to a low jitter version of the
clock and data signal outputs, reducing both deterministic and
random jitter. Several devices can be cascaded for long links
without degrading signal fidelity. Obtaining total jitter is 0.09
UI or less over the supported data rates. This low level of out-
put jitter provides system designers with extra margin and
flexibility when working with stringent timing budgets.
The transmitter supports configurable transmit de-emphasis
so the output can be optimized for driving additional lengths
of cables or FR4 traces.
Features
■ Optimized for HDMI/DVI repeater applications
■ TMDS compatible inputs with configurable receive
equalization supporting data rates up to 3.4 Gbps
■ TMDS compatible outputs with configurable transmit de-
emphasis
■ Dedicated CDR on each data channel reduces jitter
transfer, enabling multiple devices to be cascaded without
impairing signal fidelity
■ Capable of multi-hop extension of HDMI/DVI applications
at data rates between 250 Mbps and 3.4 Gbps
■ Resistor adjustable differential output voltage for AC
coupled Cat5e and Cat6 extension applications
■ 2 equalizer settings for a wide range of cable reaches at
different data rates
■ Total Output Jitter of 0.09 UI at 2.25 Gbps
■ Total Output Jitter of 0.10 UI at 3.4 Gbps
■ DVI 1.0 and HDMI v1.3a compatible TMDS source and
sink interface
■ 7 mm x 7 mm 48 pin LLP package
■ >8 kV HBM ESD protection
■ 0 °C to +70 °C operating temperature
Applications
■ Repeater Applications
— Digital Routers
— HDMI / DVI Extender Multi-hops
■ Source Applications
— Video Cards
— Blu-ray DVD Players
— Game Consoles
■ Sink Applications
— High Definition Displays
— Projectors
Application Diagram
© 2009 National Semiconductor Corporation 300873
30087353
www.national.com
1 page  
Symbol
Parameter
CwMwwL.IDnaptuaStsheet4U.com
Condition
VTX
Input Voltage
Swing (Launch
Amplitude)
Measured differentially at
TPA, Figure 1, note 4
VICMDC
Input Common-
Mode Voltage
DC-Coupled requirement
Measured at TPB,
VINmin = 800mV,
VINmax = 1200mV, Figure 1
VIN
Input Voltage
Sensitivity
Measured differentially at
TPB, Figure 1
3.4 Gbps, Clock Pattern
RIN Input resistance IN+ to VDD and IN- to VDD
RLI Differential output 100 MHz – 1125 MHz
return loss
CML Outputs
Measured DC outputs at
VOFF
Standby Output
Voltage
TPC, RT = 50Ω when DUT
VDD is off with OUT+ and
OUT- terminated by RT=
50Ω to AVCC, Figure 2
External resistor = 24 kΩ at
VOD_CRL pin.Measured
VO
Differential Output differentially with OUT+ and
voltage swing
OUT- terminated by
VOCM
Output common-
mode Voltage
RT=50Ω to AVCC, Figure 2
Measured single-ended,
>1.65 Gbps, Figures 2, 3
tR, tF
Transition time
20% to 80% of differential
output voltage, measured
within 1” from output pins,
Figure 3
tCCSK
Inter Pair Data
Channel-to-
Channel Skew (all
3 data channels)
Difference in 50% crossing
between channels
3.4 Gbps, Clock Pattern
(Note 4)
tPPSK
Inter Pair Data
Channels Part-
toPart Skew
Difference in 50% crossing
between channels of any two
devices
3.4 Gbps, Clock Pattern
tDD
Data Channels
Latency
3.4 Gbps, Clock Pattern,
Figure 4
tCD
Clock Channel
Latency
3.4 Gbps, Clock Pattern,
Figure 4
LVCMOS Outputs
tSL SD to LOCK time Figure 4
Bit Rate
fCLK
Clock Frequency
Clock Path
(Note 4)
Data Paths
bR Bit Rate (Note 4)
Min
800
VDD-0.3
150
40
AVCC - 10
800
AVCC- 0.35
25
0.25
Typ
1000
50
10
80
2
50
520
600
10
Max
1560
VDD-0.2
1560
60
Unit
mVp-p
V
mVp-p
Ohms
dB
AVCC+ 10
mV
1200
mVp-p
AVCC- 0.20
V
ps
3 ps
ps
ps
ps
ms
340 MHz
3.4 Gbps
5 www.national.com
5 Page 
RETIMING AND DE-EMPHASIS BYPASS
wwTwhe.DraetatiSmhineget4aUn.dcoDme-emphasis BYPASS pin provides the
flexibility to configure the device to an equalizer only mode.
The device is in normal operation, when holding a LOW state
on the BYPASS pin. The retiming and De-emphasis features
are disabled, when a HIGH state is applied.
CLOCK CHANNEL MODE CONTROL
During the normal operation mode, the clock channel signal
is regenerated by the PLL and the CDR. Holding a LOW state
(default) on the MODE pin places the DS34RT5110 in this
normal operation mode. A HIGH state on the MODE pin by-
passes the clock channel. This clock channel mode feature
enables the multi-hop applications. (Refer to Application In-
formation – Multiple Hop Application for detailed information)
DEVICE STATE AND ENABLE CONTROL
The DS34RT5110 has an Enable feature which provides the
ability to control device power consumption. This feature can
be controlled via the Enable Pin (EN Pin). If Enable is acti-
vated, the data channels and clock channel are placed in the
ACTIVE state and all device blocks function as described.
The DS34RT5110 can also be placed in STANDBY mode to
save power. In this mode, the output drivers of the device are
disabled. The CML outputs are in the HIGH (AVCC) state. All
LVCMOS outputs are in the HiZ state.
LOCK DETECT
When the PLL of the DS34RT5110 is locked, and the gener-
ated reference phases are successfully interpolated by the
CDR, this status is indicated by a logic HIGH on the LOCK
pin. The LOCK pin may be connected to the Enable (EN) pin
input to disable the data channels and clock channel when no
data signal is being received.
SIGNAL DETECT
The DS34RT5110 features a signal detect circuit on all chan-
nels. The status of the input signals can be determined by the
state of the SD pin. A logic HIGH indicates the presence of
signals that have exceeded a specified maximum threshold
value (called SD_ON) on all channels. A logic LOW means
that the signals have fallen below a minimum threshold value
(called SD_OFF) on one or more channels.
AUTOMATIC ENABLE FEATURE
During normal operation (i.e. BYPASS pin is LOW), the
DS34RT5110 can be configured to automatically enter
STANDBY mode, if the PLL of the DS34RT5110 is not locked.
The STANDBY mode can be implemented by connecting the
LOCK DETECT (LOCK) pin to the external (LVCMOS) En-
able (EN) pin. If the LOCK pin is connected to the EN pin, a
logic HIGH on the LOCK pin will enable the device; thus the
DS34RT5110 will automatically enter the ACTIVE state. If the
PLL is unlocked, then the LOCK pin will be asserted LOW,
causing the aforementioned blocks to be placed in the
STANDBY state.
11 www.national.com
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| PDF Descargar | [ Datasheet DS34RT5110.PDF ] | |
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