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PDF AD7192 Data sheet ( Hoja de datos )
| Número de pieza | AD7192 | |
| Descripción | 4.8 KHz Ultra-Low Noise 24-Bit Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD7192 (archivo pdf) en la parte inferior de esta página. Total 40 Páginas | ||
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4.8 kHz, Ultralow Noise, 24-Bit
Sigma-Delta ADC with PGA
AD7192
FEATURES
RMS noise: 11 nV @ 4.7 Hz (gain = 128)
15.5 noise-free bits @ 2.4 kHz (gain = 128)
Up to 22 noise-free bits (gain = 1)
Offset drift: 5 nV/°C
Gain drift: 1 ppm/°C
Specified drift over time
2 differential/4 pseudo differential input channels
Automatic channel sequencer
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
4 general-purpose digital outputs
Power supply
AVDD: 3 V to 5.25 V
DVDD: 2.7 V to 5.25 V
Current: 4.35 mA
Temperature range: –40°C to +105°C
Package: 24-lead TSSOP
Temperature measurement
Chromatography
PLC/DCS analog input modules
Data acquisition
Medical and scientific instrumentation
GENERAL DESCRIPTION
The AD7192 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can be interfaced directly to the ADC.
The device can be configured to have two differential inputs or
four pseudo differential inputs. The on-chip channel sequencer
allows several channels to be enabled, and the AD7192 sequentially
converts on each enabled channel. This simplifies communication
with the part. The on-chip 4.92 MHz clock can be used as the
clock source to the ADC or, alternatively, an external clock or
crystal can be used. The output data rate from the part can be
varied from 4.7 Hz to 4.8 kHz.
INTERFACE
3-wire serial
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Weigh scales
Strain gage transducers
Pressure measurement
The device has two digital filter options. The choice of filter
affects the rms noise/noise-free resolution at the programmed
output data rate, the settling time, and the 50 Hz/60 Hz
rejection. For applications that require all conversions to be
settled, the AD7192 includes a zero latency feature.
The part operates with a power supply from 3 V to 5.25 V. It
consumes a current of 4.35 mA. It is housed in a 24-lead TSSOP
package.
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD
DVDD DGND REFIN1(+) REFIN1(–)
AIN1
AIN2
AIN3
AIN4
AINCOM
BPDSW
AVDD
AD7192
REFERENCE
DETECT
MUX
AGND
AGND
PGA
Σ-Δ
ADC
TEMP
SENSOR
CLOCK
CIRCUITRY
SERIAL
INTERFACE
AND
CONTROL
LOGIC
DOUT/RDY
DIN
SCLK
CS
SYNC
P3
P2
MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
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Parameter
Average Reference Input Current
Drift
Normal Mode Rejection2
Common-Mode Rejection
Reference Detect Levels
TEMPERATURE SENSOR
Accuracy
Sensitivity
BRIDGE POWER-DOWN SWITCH
RON
Allowable Current2
BURNOUT CURRENTS
AIN Current
AD7192B
±0.03
±1.3
Same as for analog inputs
100
0.3
0.6
±2
2815
10
30
500
Unit
nA/V/°C typ
nA/V/°C typ
dB typ
V min
V max
°C typ
Codes/°C typ
Ω max
mA max
nA nom
DIGITAL OUTPUTS (P0 to P3)
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current2
Floating-State Output
Capacitance
INTERNAL/EXTERNAL CLOCK
Internal Clock
Frequency
Duty Cycle
External Clock/Crystal
Frequency
Input Low Voltage VINL
Input High Voltage, VINH
Input Current
LOGIC INPUTS
Input High Voltage, VINH2
Input Low Voltage, VINL2
Hysteresis2
Input Currents
LOGIC OUTPUT (DOUT/RDY)
Output High Voltage, VOH2
Output Low Voltage, VOL2
Output High Voltage, VOH2
Output Low Voltage, VOL2
Floating-State Leakage Current
Floating-State Output
Capacitance
Data Output Coding
AVDD − 0.6
0.4
4
0.4
±100
10
4.92 ± 4%
50:50
4.9152
2.4576/5.12
0.8
0.4
2.5
3.5
±10
2
0.8
0.1/0.25
±10
DVDD − 0.6
0.4
4
0.4
±10
10
Offset binary
V min
V max
V min
V max
nA max
pF typ
MHz min/max
% typ
MHz nom
MHz min/max
V max
V max
V min
V min
μA max
V min
V max
V min/V max
μA max
V min
V max
V min
V max
μA max
pF typ
AD7192
Test Conditions/Comments1
External clock.
Internal clock.
Applies after user calibration at 25°C.
Bipolar mode.
Continuous current.
Analog inputs must be buffered and chop
disabled.
AVDD = 3 V, ISOURCE = 100 μA.
AVDD = 3 V, ISINK = 100 μA.
AVDD = 5 V, ISOURCE = 200 μA.
AVDD = 5 V, ISINK = 800 μA.
DVDD = 5 V.
DVDD = 3 V.
DVDD = 3 V.
DVDD = 5 V.
DVDD = 3 V, ISOURCE = 100 μA.
DVDD = 3 V, ISINK = 100 μA.
DVDD = 5 V, ISOURCE = 200 μA.
DVDD = 5 V, ISINK = 1.6 mA.
Rev. A | Page 5 of 40
5 Page 
www.DataSheet4U.com
Pin No.
13
14
Mnemonic
AIN3
AIN4
15 REFIN1(+)
16 REFIN1(−)
17 BPDSW
18 AGND
19 DGND
20 AVDD
21 DVDD
22 SYNC
23 DOUT/RDY
24 DIN
AD7192
Description
Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with
AIN4 or as a pseudodifferential input when used with AINCOM.
Analog Input. This pin can be configured as the negative input of a fully differential input pair when used
with AIN3 or as a pseudodifferential input when used with AINCOM.
Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+)
can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is
AVDD, but the part functions with a reference from 1 V to AVDD.
Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V.
Bridge Power-Down Switch to AGND.
Analog Ground Reference Point.
Digital Ground Reference Point.
Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with
AVDD at 5 V or vice versa.
Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V
with DVDD at 5 V or vice versa.
Logic input that allows for synchronization of the digital filters and analog modulators when using a number
of AD7192 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the
calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not
affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally
to DVDD.
Serial Data Output/Data Ready Output. DOUT/RDYserves a dual purpose. It functions as a serial data output
pin to access the output shift register of the ADC. The output shift register can contain data from any of the
on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate
the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next
update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid
data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the
data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the
SCLK rising edge.
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control
registers in the ADC, with the register selection bits of the communications register identifying the
appropriate register.
Rev. A | Page 11 of 40
11 Page | ||
| Páginas | Total 40 Páginas | |
| PDF Descargar | [ Datasheet AD7192.PDF ] | |
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