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PDF AD7190 Data sheet ( Hoja de datos )
| Número de pieza | AD7190 | |
| Descripción | 4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
FEATURES
RMS Noise: 7 nV @ 4.7 Hz (gain = 128)
16.5 noise free bits @ 2.4 kHz (gain = 128)
Up to 23 noise free bits (gain = 1)
Offset drift: 5 nV/°C
Gain drift: 2 ppm/°C
Specified drift over time
Programmable gain (1 – 128)
Update rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
Four general purpose digital outputs
Power supply: 3 V to 5.25 V
Current: 6 mA
Temperature range: –40°C to +105°C
INTERFACE
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Weigh scales
Strain gauge transducers
Pressure measurement
Temperature measurement
Chromatography
4.8 kHz Ultra-Low Noise 24-Bit
Sigma-Delta ADC with PGA
AD7190
PLC/DCS Analog Input Modules
Data Acquisition
Medical and Scientific instrumentation
GENERAL DESCRIPTION
The AD7190 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise, 24-
bit ∑-∆ ADC. The on-chip low noise gain stage means that
signals of small amplitude can be interfaced directly to the
ADC.
The device can be configured to have two differential inputs or
four pseudo-differential inputs. The device can be operated
with either the internal clock or an external clock. The output
data rate from the part can be varied from 4.7 Hz to 4.8 kHz.
The device can be operated with a sinc3 or a sinc4 digital filter.
At the lower update rates, the sinc3 is useful to optimize the
settling time. The benefit of the sinc4 at low update rates is the
superior 50 Hz/60 Hz rejection. At the higher update rates, the
sinc4 filter gives best noise performance. For applications that
require all conversions to be settled, the AD7190 includes a
zero-latency feature.
The part operates with a power supply from 3 V to 5.25 V. It
consumes a current of 6 mA. It is housed in a 24-lead TSSOP
package.
AVDD
FUNCTIONAL BLOCK DIAGRAM
AGND
DVDD DGND
REFIN1(+) REFIN1(-)
AIN1
AIN2
AIN3
AIN4
AINCOM
BPDSW
AGND
AD7190
AVDD
MUX
PGA
SIGMA DELTA
ADC
AGND
TEMP
SENSOR
CLOCK
CIRCUITRY
REFERENCE
DETECT
SERIAL
INTERFACE
AND CONTROL
LOGIC
DOUT/RDY
DIN
SCLK
CS
SYNC
P3
P2
MCLK1
MCLK2
Figure 1.
P0/REFIN2(-) P1/REFIN2(+)
Rev.PrD
7/08
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2008 Analog Devices, Inc. All rights reserved.
1 page  
www.DParteaSlihmeeint4aUr.cyomTechnical Data
AD7190
TIMING CHARACTERISTICS
AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 2.
Parameter1, 2
t3
t4
Read Operation
t1
t23
t55, 6
t6
t7
Write Operation
t8
t9
t10
t11
Limit at TMIN, TMAX (B Version)
100
100
0
60
80
0
60
80
10
80
0
10
0
30
25
0
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK high pulse width
SCLK low pulse width
CS falling edge to DOUT/RDY active time
DVDD = 4.75 V to 5.25 V
DVDD = 2.7 V to 3.6 V
SCLK active edge to data valid delay4
DVDD = 4.75 V to 5.25 V
DVDD = 2.7 V to 3.6 V
Bus relinquish time after CS inactive edge
SCLK inactive edge to CS inactive edge
SCLK inactive edge to DOUT/RDY high
CS falling edge to SCLK active edge setup time4
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
CS rising edge to SCLK edge hold time
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2 See Figure 3 and Figure 4.
3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4 SCLK active edge is falling edge of SCLK.
5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
ISINK (1.6mA WITH DVDD = 5V,
100µA WITH DVDD = 3V)
TO
OUTPUT
PIN
50pF
1.6V
ISOURCE (200µA WITH DVDD = 5V,
100µA WITH DVDD = 3V)
Figure 2. Load Circuit for Timing Characterization
Rev.PrD 7/08 | Page 5
5 Page 
www.DParteaSlihmeeint4aUr.cyomTechnical Data
CHOP ENABLED
Table 7 shows the AD7190’s rms noise for some of the update
rates and gain settings. The numbers given are for the bipolar
input range with an external 5 V reference. These numbers are
typical and are generated with a differential input voltage of 0 V.
Table 8 shows the effective resolution, while the output peak-to-
peak (p-p) resolution is listed in brackets. It is important to note
AD7190
that the effective resolution is calculated using the rms noise,
while the p-p resolution is calculated based on peak-to-peak
noise. The p-p resolution represents the resolution for which
there will be no code flicker. These numbers are typical and are
rounded to the nearest half-LSB.
Table 7. RMS Noise (nV) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop Enabled
Filter
Word
(Decimal)
Update
Rate (Hz)
Gain of 1
Gain of 8
Gain of 16 Gain of 32 Gain of 64 Gain of 128
1023
1.175
123
17.47
8.94
7.07
5.87
5
640
1.875
138
21.41
10.27
8.68
7.33
7.07
480 2.5
174
26.87
13.67
10
8.49 7.25
96
12.5 395
61.52
31.11
25.22
19.64
17.9
16
75
950
132
74.25
51.5
48.49
37.24
2
600
3008
412
228
164
141
118
1
1200
9192
1255
636
479
351
266
Table 8. Typical Resolution (Bits) vs. Gain and Output Update Rate (continuous conversion mode) Using a 5 V Reference - Chop
Enabled
Filter Word Update
(Decimal) Rate (Hz)
Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128
1023
1.175
24 (23.5) 24 (23.5) 24 (23.5) 24 (22.5) 24 (22)
24 (21.5)
640
1.875
24 (23.5) 24 (23)
24 (23)
24 (22.5) 24 (21.5) 23.5 (21)
480 2.5
24 (23)
24 (22.5) 24 (22.5) 24 (22)
24 (21.5) 23 (20.5)
96
12.5
24 (22)
24 (21.5) 24 (21.5) 23.5 (21) 23 (20.5) 22 (19.5)
16 75 23.5 (21) 23 (20.5) 23 (20.5) 22.5 (20) 21.5 (19) 21 (18.5)
2 600 21.5 (19) 21.5 (19) 21.5 (19) 21 (18.5) 20 (17.5) 19.5 (17)
1
1200
20 (17.5) 20 (17.5) 20 (17.5) 19.5 (17) 18.5 (16) 18 (15.5)
Rev.PrD 7/08 | Page 11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AD7190.PDF ] | |
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