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PDF NJW1192 Data sheet ( Hoja de datos )
| Número de pieza | NJW1192 | |
| Descripción | Electronic Volume / SSOP32 | |
| Fabricantes | JRC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de NJW1192 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
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NJW1192
4-channel Electronic Volume with Input Selector
!GENERAL DESCRIPTION
NJW1192 is 4-channel Electronic Volume with input
selector. It includes main volume, balance and fader trim, 3
stereo inputs and 1 mono input selector, loudness and tone
control.
NJW1192 performs low noise and low distortion
characteristics with resistance ladder type electrical volume.
All of internal status and variables are controlled by I2C BUS
interface.
!PACKAGE OUTLINE
NJW1192V
!FEATURES
●Operating Voltage
7.5 to 13V
●I2C BUS Interface
●Low Output Noise
-103dBVtyp
●Low Distortion
0.005%typ
●3ch Stereo & 1ch Monaural Input Selector
●Tone Control
Bass / Treble
●Main Volume
●Balance & Fader
●Bi-CMOS Technology
●Package Outline
SSOP32
!BLOCK DIAGRAM
MONO
0, +6dB,
+12 dB, +18dB
0, +6dB,
+12 dB, +18dB
Treble Bass
Treble Bass
I2C
Interface
Bias
–1–
1 page  
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NJW1192
s I2C BUS CHARACTERISTICS (SDA, SCL)
I2C BUS Load Conditions
STANDARD MODE :
Pull up resistance 4k
FAST MODE :
Pull up resistance 4k
(Connected to +5V), Load capacitance 200pF (Connected to GND)
(Connected to +5V), Load capacitance 50pF (Connected to GND)
PARAMETER
Standard mode
Fast mode
SYMBOL
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
Low Level Input Voltage
VIL
0.0 - 1.5 0.0 - 1.5
V
High Level Input Voltage
VIH
2.5 - 5.5 2.5 - 5.5
V
Hysteresis of Schmitt trigger inputs
Vhys - - - 0.25 - - V
Low level output voltage (3mA at SDA pin)
Output fall time from VIHmin to VILmax with
a bus capacitance from 10pF to 400pF
Pulse width of spikes which must be suppressed
by the input filter
Input current each I/O pin with an input voltage
between 0.1VDD and 0.9VDDmax
Capacitance for each I/O pin
VOL
tof
tSP
Ii
Ci
0 - 0.4 0 - 0.4 V
-
- 250 20
- 250
ns
+0.1Cb
- - - 0 - 50 ns
-10 -
10 -10
-
10
µA
- - 10 - - 10 pF
SCL clock frequency
fSCL - - 100 - - 400 kHz
Hold time (repeated) START condition.
tHD:STA 4.0 - - 0.6 - - µs
Low period of the SCL clock
tLOW
4.7 -
- 1.3 -
-
µs
High period of the SCL clock
tHIGH
4.0 -
- 0.6 -
-
µs
Set-up time for a repeated START condition
tSU:STA 4.7 - - 0.6 - - µs
Data hold time
tHD:DAT 0 - - 0 - - µs
Data set-up time
tSU:DAT
250
-
- 100 -
-
ns
Rise time of both SDA and SCL signals
tr - - 1000 - - 300 ns
Fall time of both SDA and SCL signals
tf - - 300 - - 300 ns
Set-up time for STOP condition
tSU:STO 4.0 - - 0.6 - - µs
Bus free time between a STOP and START condition
tBUF
4.7 -
- 1.3 -
-
µs
Capacitive load for each bus line
Cb - - 400 - - 400 pF
Noise margin at the Low level
VnL 0.5 - - 0.5 - -
V
Noise margin at the High level
VnH 1 - - 1 - - V
Cb ; total capacitance of one bus line in pF.
SDA
tf
tr
SCL
tHD:STA
S
tLOW
tSU:DAT
tf
tHD:STA
tHD:DAT
tHIGH
tSU:STA
Sr
tSP tr
tBUF
tSU:STO
P
S
–5–
5 Page 
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!TERMINAL DESCRIPTION
No. SYMBOL
FUNCTION
31 INMONO Monaural Input
NJW1192
EQUIVALENT CIRCUIT
V+
50 36k
60k
GND
V+
VREF
50 36k
60k
GND
VREF
VOLTAGE
V+/2
– 11 –
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet NJW1192.PDF ] | |
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