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PDF NJM2671 Data sheet ( Hoja de datos )
| Número de pieza | NJM2671 | |
| Descripción | Stepper Motor / DIP16-D2 / EMP16-E2 | |
| Fabricantes | JRC | |
| Logotipo |  |
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STEPPER MOTOR CONTROLLER / DRIVER
NJM2671
s GENERAL DESCRIPTION
s PACKAGE OUTLINE
NJM2671 is a two-phase unipolar stepping motor driver
with a motor output of a maximum of 60 V and a maximum
current of 500 mA.
The Step&Dir (Pulse Input) system of the motor controller
enables simple switching between half and full step modes.
A high voltage of 60 v and wide power voltage supply
range makes possible use with high-speed motor
applications and the high voltage improves reliability.
NJM2671D2
NJM2671E2
s FEATURES
• Maximum motor power supply voltage: 60 V
• Continuous output current: 2 ch x 500 mA
• Internal driver and phase logic
• External phase logic reset terminal (RESET)
• Phase origin monitoring output terminal (MO)
• Thermal shutdown circuit
• Package DIP16 ,EMP16
s PIN CONFIGURATIONS
PB2 1
PB1 2
GND 3
PA1 4
PA2 5
DIR 6
STEP 7
φB 8
NJM
2671D2
16 VCC
15 MO
14 RESET
13 NC
12 NC
11 INH
10 HSM
9 φA
PB2 1
PB1 2
GND 3
PA1 4
PA2 5
DIR 6
STEP 7
φB 8
Fig.1 Pin Configurations
NJM
2671E2
16 VCC
15 MO
14 RESET
13 NC
12 NC
11 INH
10 HSM
9 φA
Ver.2004-09-25
-1-
1 page  
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the timing chart in Figure 4.
NJM2671
• INH – phase output off
All phase output is turned off when INH goes high reducing power consumption (consumption current).
• RESET
A two-phase stepping motor repeats the same winding energizing sequence every angle that is a multiple of
four of the basic step. The phase logic sequence is repeated every four pulses in the full step mode and every
eight pulses in the half step mode.
RESET forces to initialize the phase logic to sequence start mode.
When RESET is at L level, the phase logic is initialized and the phase output is turned off.
When RESET recovers to H level, the phase output resumes the energizing pattern output at sequence
start of phase logic. Refer to Figure 5 for a reset timing chart.
sPOR – power on and reset function
The internal power-on and reset circuit, which is connected to Vcc, resets the phase logic and turns off phase
output when the power is supplied to prevent missteps.
Each time the power is turned on, the energizing pattern of phase logic at sequence start is output.
s Phase output unit
The phase output unit is composed of four open collector transistors that are directly connected to the stepping
motor as shown in Figure 3.
s ΦA, ΦB bi-polar phase logic output
This ΦA, ΦB output is a signal generated by the phase logic for external monitoring to determine whether the
energizing sequence is 1-phase or 2-phase energizing. Missteps normally occur unless the switch from half step
to full step mode is performed appropriately. Use of ΦA, ΦB output switches HSM in 2-phase energizing status
(ΦA = ΦB = L level) enables switching between the half and full step modes without missteps.
s MO – origin monitor
At sequence start of the phase logic or after POR or external RESET, an L level output is made to indicate to
external devices that the energizing sequence is in initial status.
HSM,DIR
Vcc
STEP
approx 3.0V∼ 4.0V
STEP,RESET
Ip
ts tp
td
Fig.4 Timing chart
RESET
PB1/PA1
PB2/PA
POR function
Normal
sequence
Phase
output OFF
Normal
sequence
After internal phase
logic initialize output
Fig.5 POR and external reset timing
Ver.2004-09-25
-5-
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet NJM2671.PDF ] | |
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