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PDF NJU26901 Data sheet ( Hoja de datos )

Número de pieza NJU26901
Descripción Delay
Fabricantes JRC 
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NJU26901
Digital Audio Delay
General Description
Package
The NJU26901 is a digital audio delay. The NJU26901 provides delay-time
adjustment function and digital audio interface.
FEATURES
NJU26901E2 NJU26901M
2-Channel Audio Delay (24 bits data width).
Delay Time 85msec at fs = 48kHz ( 128msec at fs = 32kHz , 43msec at fs = 96kHz)
4 delay time modes( ¼, ½, ¾, 1 max. delay ) are selectable without a micro-computer.
To make long delay time, the NJU26901 can be connected serially.
Non-audio-signal data can be delayed by the NJU26901.
Hardware Specification
Digital Audio Interface
Digital Audio Format
Audio Bit Clock (BCK) Frequency
Package
Power Supply
: 1 Input port / 1 Output port
: I2S 24bit BCK : 64fs, Slave Mode
: 13MHz Max ( approximate fs=200KHz)
: EMP8, DMP8 ( Pb-Free )
: 2.5V ( +3.3V input tolerant )
Function Block Diagram
LRI
BCKI
SDI
SERIAL
AUDIO
INTERFACE
L/R in
NJU26901
BCKI
LRI
Delay
RAM
SERIAL
AUDIO
INTERFACE
L/R out
Control
Logic
COUNT[1:0]
Fig. 1 Function Block Diagram
SDO
Ver.2007-01-31
-1-

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NJU26901 pdf
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NJU26901
Serial Audio Interface
Digital Audio format is I2S 24bit 64fs in fig. 5. The input and output format are the same I2S 24bit 64fs.
LRI
BCKI
SDI, SDO
Left Channel
Right Channel
MSB LSB
23 2221 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB LSB
23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
Fig 5 Digital Audio Format (I2S 24bits 64fs)
Function Description
SDI(#1) is serial audio input pin. The input audio data should be connected to this pin. The NJU26901 fetches
in the input audio data every LRI edge.
LRI(#2) is LR clock input pin. This LR clock frequency is the same frequency of the input audio signal.
LRI=”Low” shows SDI and SDO data are left channel data. LRI=”High” shows SDI and SDO data are right
channel data.
BCKI(#3) is bit clock input pin. This BCKI clock frequency is 64 times as large as the input audio signal.
SDO(#7) is serial audio output pin. The delayed audio data come out through this pin.
VDD(#8) is 2.5V power supply pin. VSS(#4) is GND pin. The decoupling capacitor is necessary between VDD
and VSS.
The input pins can interface to 3.3V ICs. The output pins can interface to 2.5V ICs. Refer to table3 “Electric
Characteristics”.
After Power-on RESET, there is possibility the NJU26901 generates random data for the delay time period set
by COUNT[0],[1] pins. If necessary, the mute circuit should be added.
Delay Time
The NJU26901 provides maximum 4097 samples delay and slave-mode audio interface. The delay time
depends on sampling frequency.
Delay time is controlled by COUNT[0], COUNT[1]. Table 5 shows Delay Time vs Sampling Frequency.
Detail delay time is evaluated by the following formula.
Delay time = {1/(fs)} × (sampling number + 1)
[sec]
The sampling number is incremented every LRI clock.
Table 5 Delay Time vs Sampling Frequency
Sampling Frequency
4/4
3/4
(fs)
(COUNT[1:0]=11)
(COUNT[1:0]=01)
192KHz
21ms
16ms
96KHz
43ms
32ms
88.2KHz
47ms
35ms
48KHz
85ms
64ms
44.1KHz
93ms
69ms
32KHz
128ms
96ms
Sampling number
(4097)
(3073)
1/2
(COUNT[1:0]= 10)
11ms
21ms
23ms
43ms
46ms
64ms
(2049)
1/4
(COUNT[1:0]= 00)
5ms
11ms
12ms
21ms
23ms
32ms
(1025)
Ver.2007-01-31
-5-

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