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PDF NJU3430 Data sheet ( Hoja de datos )
| Número de pieza | NJU3430 | |
| Descripción | 16 characters 1 line / QFP64-G1 | |
| Fabricantes | JRC | |
| Logotipo |  |
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NJU3430
16-CHARACTER 1-LINE DOT MATRIX VFD CONTROLLER DRIVER
n GENERAL DESCRIPTION
The NJU3430 is a Dot Matrix VFD (Vacuum Fluorescent Display)
Controller Driver for 16-character 1-line with Icon display.
It contains character generator ROM/RAM, address counter, oscilla-
tion circuit, command register, Icon display RAM, high voltage drivers,
and serial interface circuit.
The display data or the command data is transmitted with the serial
interface circuits.
The character generator consists of 8,400 bits ROM and 35 x 8 bits
RAM. The CG RAM stores 8 kinds of character by 5 x 7dots maxi-
mum.
The 16-common and 37-segment (35 for character, 2 for icon) drivers
operated up to 45V drive the display of 16-character 1-line with 32-
Icon.
Furthermore, the NJU3430 incorporates one Output port which drives
the LED.
n PACKAGE OUTLINE
NJU3430FG1
n FEATURES
l 16-character 1-line Dot Matrix VFD Controller Driver
l Serial Interface with Microprocessor
l Display Data RAM
16 x 8 bits : 16-character 1-line Display
l Character Generator ROM
8,400 bits : 240 Characters for 5 x 7 Dots
l Character Generator RAM
35 x 8 bits : 8 Patterns (5 x 7 Dots)
l Icon Display RAM
16 x 2 bits : Maximum 32 Icon
l VFD Driving Voltage
| VDD-VFDP | ≤ 45V
Timing Signal
: 16
Segment Signal : 35 (Except for Icon Segment Signal)
l Output Port for LED : 1
l Display ON/OFF Function
l Digit Scan Function
l Display Duty (Contrast Control) : 8-step (8/16 to 15/16)
l Character / Icon Shift Function
l Display Mode (9 to 16 Digits)
l Oscillation Circuit on-chip (External Resistor and Capacitor Required)
l Operating Voltage
3.0V to 5.5V (Except VFD Driving Voltage)
l Package Outline
QFP 64
l C-MOS Technology
Jul. 2003
Ver. 3
1 page  
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NJU3430
Table 2.CG ROM Character Pattern (ROM version -02)
5 Page 
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NJU3430
(h)RAM Address Set
RS B7 B6 B5 B4 B3 B2 B1 B0
1 0 0 0 A D 3 A D 2 A D 1 A D 0 ← DD RAM Addredd Set:(00)H to (0F)H
0 1 0 0 1 A M 3 A M 2 A M 1 A M 0 ← MK RAM Address Set:(00)H to (0F)H
1 1 A C 5 A C 4 A C 3 A C 2 A C 1 A C 0 ← CG RAM Address Set:(00)H to (3F)H
The DD RAM, MK RAM and CG RAM Address are set by RAM Address Set. Correspondences of each RAM
address and Display position are shown below :
Correspondence of DD RAM Address and Timing terminals (Not shift)
DD RAM Address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
Digits
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Correspondence of MK RAM Address and Timing terminals (Not shift)
MK RAM Address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
Digits
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
About the detail of CG RAM Address, refer to "(1)CG RAM data and Character Dot Matrix”.
(i)Write Data to RAM
RS B7 B6 B5 B4 B3 B2 B1 B0
S D 7 S D 6 S D 5 S D 4 S D 3 S D 2 S D 1 S D 0 ← DD RAM Data Set:(00)H to (FF)H
1 0 0 0 0 0 0 S M 1 S M 0 ← MK RAM Data Set:(00)H to (03)H
0 0 0 S C 4 S C 3 S C 2 S C 1 S C 0 ← CG RAM Data Set:(00)H to (1F)H
The data are written into DD RAM, MK RAM and CG RAM by Write Data to RAM. The writing data address is
used that is set the address just before writing data. Therefore, when the new data writing, the address set should
be executed before writing data. The address is increased by 1 automatically after writing data, therefore, the MPU
writes the data into the each RAM without any address setting after the start address.
(Writing example)
1Byte
10000011
DD RAM Address
set(03)H
2Byte
3Byte
4Byte
01010101
11111000
00110101
DD RAM Address(03)H DD RAM Address(04)H DD RAM Address(05)H
set CG ROM(55)H
set CG ROM(F8)H set CG ROM(35)H
The writing data in the each RAM are shown below.
DD RAM Data[SD7 to SD0] --- Character code of each digit
: (00)H to (FF)H
MK RAM Data[SM1 to SM0] --- Icon display of each digit
: SM1→MK2, SM0→MK1
CG RAM Data[SC4 to SC0] --- Character code
: (00)H to (0F)H Dot Data
(About the detail, refer to "(1)CG RAM data and Character Dot Matrix”.)
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet NJU3430.PDF ] | |
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