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PDF NJU7333 Data sheet ( Hoja de datos )
| Número de pieza | NJU7333 | |
| Descripción | FAN Motor / VSP10 | |
| Fabricantes | JRC | |
| Logotipo |  |
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NJU7333
Single-phaseDC Brushless Motor Driver IC
s GENERAL DESCRIPTION
s PACKAGE OUTLINE
The NJU7333 is a single-phase DC brushless motor
driver IC for small fan-motor and high power applications. It
features MOS-FET driver circuit for better saturation
characteristics. Slew late of amplifiers and feedback
resistors are optimized to achieve low-noise motor
operation. Maximum output current is 500mA. The
NJU7333 includes. frequency generator (FG) output, lock
detect (with auto recovery circuit) ,and a thermal shutdown
circuit .
NJU7333R
s FEATURES
• Operating Voltage VDD=2.4 ∼ 5.5V
• FG Output
• Internal Lock Detect / Auto Recovery Circuit
• Internal Thermal Shutdown Circuit
• Low Operating Current IDD=3mA (Typ.)
• Low Saturation Output Voltage
Vsat=±0.35V @Io=±500mA
• C-MOS Technology
• Package Outline VSP10
s BLOCK DIAGLAM
s PIN FUNCTION
1:Ct
2: FG
3: Vdd
4: OUT B
5: Vss
6: Vss
7: OUT A
8: Vdd
9: IN-
10: IN+
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Lock detection time (Ton) is given by:
NJU7333
Preliminary
[ ]TON
= C 2 VCL − VID
ICHG
sec
Where C2 is 0.47uF:
TON
=
0.47
×10
−
6
×
2.6 − 0.6
1.5 ×10−6
= 0.62[sec]
Auto Resume Time (Toff) is given by:
[ ]TOFF
= C 2 VCL − VID
IDCHG
sec
Where C2 is 0.47uF:
TOFF
=
0.47
×10
−6
×
2.6 − 0.6
0.5 ×10−6
= 1.88[sec]
In actual application, Lock detection time (Ton) is affected by the mechanical time constant of a motor. Therefore,
constant start up must be confirmed in actual evaluation taking operating variations (i.e.Temperature, Voltage change
and so on) in consideration.
A typical value of C2 is either 0.47uF or 1uF depending on a motor.
Hall input
Motor output
Ct Terminal voltage
Toff Ton
Motor Lock protection period
Motor Locked
Returns to normal operation
3. Design of hall element bias resistance (R1 and R2)
Hall amplifier is a differential amplifier with hysteresis characteristics (24mV typical).
The common-mode input voltage is between 0.4V and VDD-1V and the input signal must be within the
range.Non-excitation hall bias voltage is to be set at a half of VDD for effective use of common-mode input voltage
range. Therefore the same value of hall bias resistors is selected for R1 and R2.
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5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet NJU7333.PDF ] | |
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