PDF ADN4665 Data sheet ( Hoja de datos )

Número de pieza	ADN4665
Descripción	CMOS Differential Line Driver
Fabricantes	Analog Devices
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No Preview Available ! www.DataSheet4U.com FEATURES ±15 kV ESD protection on output pins 400 Mbps (200 MHz) switching rates 100 ps typical differential skew 400 ps maximum differential skew 2 ns maximum propagation delay 3.3 V power supply ±350 mV differential signaling Low power dissipation (13 mW typical) Interoperable with existing 5 V LVDS receivers High impedance on LVDS outputs on power-down Conforms to TIA/EIA-644 LVDS standards Industrial operating temperature range: −40°C to +85°C Available in surface-mount SOIC package and low profile TSSOP package APPLICATIONS Backplane data transmission Cable data transmission Clock distribution GENERAL DESCRIPTION The ADN4665 is a quad-channel, CMOS, low voltage differential signaling (LVDS) line driver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. The device accepts low voltage TTL/CMOS logic signals and converts them to a differential current output of typically ±3.5 mA for driving a transmission medium such as a twisted pair cable. The transmitted signal develops a differential voltage of typi- cally ±350 mV across a termination resistor at the receiving end. This voltage is converted back to a TTL/CMOS logic level by an LVDS receiver. 3 V, LVDS, Quad, CMOS Differential Line Driver ADN4665 FUNCTIONAL BLOCK DIAGRAM ADN4665 VCC DIN1 DIN4 D1 D4 DOUT1+ DOUT1– EN DOUT4+ DOUT4– EN DOUT2– DOUT2+ DIN2 GND D2 D3 Figure 1. DOUT3– DOUT3+ DIN3 The ADN4665 also offers active high and active low enable/ disable inputs (EN and EN). These inputs control all four drivers and turn off the current outputs in the disabled state to reduce the quiescent power consumption to typically 10 mW. The ADN4665 offers a new solution to high speed, point-to-point data transmission and offers a low power alternative to emitter- coupled logic (ECL) or positive emitter-coupled logic (PECL). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. 1 page www.DataSheet4U.com DINx DOUTx– DOUTx+ tPLHD VOD tPHLD 3V 1.5V 0V VOH 0V (DIFFERENTIAL) VOL VDIFF VDIFF = DOUTx+ – DOUTx– 80% 0V 20% tTLH tTHL Figure 4. Driver Propagation Delay and Transition Time Waveforms VCC VCC DINx S1 SIGNAL GENERATOR 50Ω EN EN DOUTx+ CL 50Ω 1.2V 50Ω DOUTx– CL NOTES 1. CL INCLUDES LOAD AND TEST JIG CAPACITANCE. 2. S1 CONNECTED TO VCC FOR tPHZ AND tPZH TEST. 3. S1 CONNECTED TO GND FOR tPLZ AND tPZL TEST. Figure 5. Test Circuit for Driver Three-State Delay EN WITH EN = GND OR OPEN CIRCUIT EN WITH EN = VCC DOUTx+ WITH DINx = VCC OR DOUTx– WITH DINx = GND tPHZ tPZH DOUTx+ WITH DINx = GND OR DOUTx– WITH DINx = VCC tPLZ tPZL Figure 6. Driver Three-State Delay Waveforms 3V 1.5V 0V 3V 1.5V 0V VOH 50% 1.2V 1.2V 50% VOL Rev. 0 \| Page 5 of 12 ADN4665 5 Page www.DataSheet4U.com NOTES ADN4665 Rev. 0 \| Page 11 of 12 11 Page

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