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PDF ADN4663 Data sheet ( Hoja de datos )

Número de pieza ADN4663
Descripción LVDS High Speed Differential Driver
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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FEATURES
±15 kV ESD protection on output pins
600 Mbps (300 MHz) switching rates
Flow-through pinout simplifies PCB layout
300 ps typical differential skew
700 ps maximum differential skew
1.5 ns maximum propagation delay
3.3 V power supply
±355 mV differential signaling
Low power dissipation: 23 mW typical
Interoperable with existing 5 V LVDS receivers
Conforms to TIA/EIA-644 LVDS standard
Industrial operating temperature range (−40°C to +85°C)
Available in surface-mount (SOIC) package
APPLICATIONS
Backplane data transmission
Cable data transmission
Clock distribution
GENERAL DESCRIPTION
The ADN4663 is a dual, CMOS, low voltage differential
signaling (LVDS) line driver offering data rates of over
600 Mbps (300 MHz), and ultralow power consumption.
It features a flow-through pinout for easy PCB layout and
separation of input and output signals.
The device accepts low voltage TTL/CMOS logic signals and
converts them to a differential current output of typically
±3.1 mA for driving a transmission medium such as a
Dual, 3 V, CMOS, LVDS
High Speed Differential Driver
ADN4663
FUNCTIONAL BLOCK DIAGRAM
VCC
DIN1
ADN4663
DOUT1+
DOUT1–
DIN2
DOUT2+
DOUT2–
GND
Figure 1.
twisted-pair cable. The transmitted signal develops a differential
voltage of typically ±355 mV across a termination resistor at the
receiving end, and this is converted back to a TTL/CMOS logic
level by a line receiver.
The ADN4663 and a companion receiver offer a new solution
to high speed point-to-point data transmission, and a low
power alternative to emitter-coupled logic (ECL) or positive
emitter-coupled logic (PECL).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.

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ADN4663 pdf
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Test Circuits and Timing Diagrams
VCC
VCC
DINx
DOUTx+
RL/2
RL/2
VOS VOD
VV
DOUTx–
Figure 2. Test Circuit for Driver VOD and VOS
SIGNAL
GENERATOR
VCC
DINx
50
DOUTx+
CL
RL
DOUTx–
CL
CL INCLUDES LOAD AND TEST JIG CAPACITANCE.
Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency
DINx
DOUTx–
DOUTx+
1.5V
tPLHD
0V (DIFFERENTIAL) VOD
1.5V
tPHLD
0V
3V
0V
VOH
VOL
VDIFF
80%
80%
0V
VDIFF = DOUT+ – DOUT–
0V
20%
20%
tTHL
tTHL
Figure 4. Driver Propagation Delay and Transition Time Waveforms
ADN4663
Rev. 0 | Page 5 of 12

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THEORY OF OPERATION
The ADN4663 is a dual line driver for low voltage differential
signaling. It takes a single-ended 3 V logic signal and converts
it to a differential current output. The data can then be transmitted
for considerable distances, over media such as a twisted-pair cable
or PCB backplane, to an LVDS receiver, where it develops a voltage
across a terminating resistor, RT. This resistor is chosen to match
the characteristic impedance of the medium, typically around
100 Ω. The differential voltage is detected by the receiver and
converted back into a single-ended logic signal.
When DINx is high (Logic 1), current flows out of the DOUTx+ pin
(current source) through RT and back into the DOUTx− pin (current
sink). At the receiver, this current develops a positive differential
voltage across RT (with respect to the inverting input) and results
in a Logic 1 at the receiver output. When DINx is low, DOUTx+
sinks current and DOUTx− sources current; a negative differential
voltage across RT results in a Logic 0 at the receiver output.
The output drive current is between ±2.5 mA and ±4.5 mA
(typically ±3.55 mA), developing between ±250 mV and ±450 mV
across a 100 Ω termination resistor. The received voltage is centered
around the receiver offset of 1.2 V. Therefore, the noninverting
receiver input is typically (1.2 V + [355 mV/2]) = 1.377 V, and
the inverting receiver input is (1.2 V − [355 mV/2]) = 1.023 V
for Logic 1. For Logic 0, the inverting and noninverting output
voltages are reversed. Note that because the differential voltage
reverses polarity, the peak-to-peak voltage swing across RT is
twice the differential voltage.
Current mode drivers offer considerable advantages over
voltage mode drivers such as RS-422 drivers. The operating
current remains fairly constant with increased switching
frequency, whereas that of voltage mode drivers increase
exponentially in most cases. This is caused by the overlap
as internal gates switch between high and low, which causes
currents to flow from the device power supply to ground.
ADN4663
A current mode device simply reverses a constant current
between its two outputs, with no significant overlap currents.
This is similar to emitter-coupled logic (ECL) and positive
emitter-coupled logic (PECL), but without the high quiescent
current of ECL and PECL.
APPLICATIONS INFORMATION
Figure 21 shows a typical application for point-to-point data
transmission using the ADN4663 as the driver and a LVDS
receiver.
0.1µF
VCC
+3.3V
+ 10µF
TANTALUM
+3.3V
+
VCC
DINx
ADN4663
DOUTx+
RT
100
DOUTx–
DIN+
DIN–
LVDS RECEIVER
DOUT
GND
GND
Figure 21. Typical Application Circuit
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