PDF ADN4667 Data sheet ( Hoja de datos )

Número de pieza	ADN4667
Descripción	3V LVDS Quad CMOS Differential Line Driver
Fabricantes	Analog Devices
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No Preview Available ! www.DataSheet4U.com FEATURES ±15 kV ESD protection on output pins 400 Mbps (200 MHz) switching rates Flow-through pinout simplifies PCB layout 300 ps typical differential skew 400 ps maximum differential skew 1.7 ns maximum propagation delay 3.3 V power supply ±310 mV differential signaling Low power dissipation (10 mW typical) Interoperable with existing 5 V LVDS receivers High impedance on LVDS outputs on power-down Conforms to TIA/EIA-644 LVDS standard Industrial operating temperature range: −40°C to +85°C Available in low profile TSSOP package APPLICATIONS Backplane data transmission Cable data transmission Clock distribution GENERAL DESCRIPTION The ADN4667 is a quad, CMOS, low voltage differential signaling (LVDS) line driver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow-through pinout for easy PCB layout and separation of input and output signals. The device accepts low voltage TTL/CMOS logic signals and converts them to a differential current output of typically ±3.1 mA for driving a transmission medium such as a twisted pair cable. The transmitted signal develops a differential voltage of typi- cally ±310 mV across a termination resistor at the receiving end. This is converted back to a TTL/CMOS logic level by an LVDS receiver. 3 V LVDS Quad CMOS Differential Line Driver ADN4667 FUNCTIONAL BLOCK DIAGRAM VCC ADN4667 DIN1 D1 DOUT1+ DOUT1– DIN2 DOUT2+ D2 DOUT2– DIN3 DOUT3+ D3 DOUT3– DIN4 EN EN DOUT4+ D4 DOUT4– GND Figure 1. The ADN4667 also offers active high and active low enable/ disable inputs (EN and EN). These inputs control all four drivers and turn off the current outputs in the disabled state to reduce the quiescent power consumption to typically 10 mW. The ADN4667 and a companion LVDS receiver offer a new solution to high speed, point-to-point data transmission, and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. 1 page www.DataSheet4U.com TEST CIRCUITS VCC DIN DOUT+ RL/2 RL/2 V VOS V VOD DRIVER IS ENABLED DOUT– Figure 2. Test Circuit for Driver VOD and VOS DIN DOUT– DOUT+ tPLHD VOD ADN4667 SIGNAL GENERATOR VCC DIN 50Ω CL CL DOUT+ DOUT– DRIVER IS ENABLED NOTES 1. CL INCLUDES LOAD AND TEST JIG CAPACITANCE. Figure 3. Test Circuit for Driver Propagation Delay and Transition Time tPHLD 3V 1.5V 0V VOH 0V (DIFFERENTIAL) VOL VDIFF VDIFF = DOUT+ – DOUT– 80% 0V 20% tTLH tTHL Figure 4. Driver Propagation Delay and Transition Time Waveforms VCC DIN SIGNAL GENERATOR 50Ω EN EN CL 50Ω 50Ω CL DOUT+ 1.2V DOUT– Figure 5. Test Circuit for Driver Three-State Delay EN WITH EN = GND OR OPEN-CIRCUIT EN WITH EN = VCC DOUT+ WITH DIN = VCC OR DOUT– WITH DIN = GND DOUT+ WITH DIN = GND OR DOUT– WITH DIN = VCC tPHZ tPLZ tPZH tPZL 3V 1.5V 0V 3V 1.5V 0V VOH 50% 1.2V 1.2V 50% VOL Figure 6. Driver Three-State Delay Waveforms Rev. 0 \| Page 5 of 12 5 Page www.DataSheet4U.com THEORY OF OPERATION The ADN4667 is a quad line driver for low voltage differential signaling. It takes a single-ended 3 V logic signal and converts it to a differential current output. The data can then be trans- mitted for considerable distances, over media such as a twisted pair cable or PCB backplane, to an LVDS receiver, where it devel- ops a voltage across a terminating resistor, RT. This resistor is chosen to match the characteristic impedance of the medium, typically around 100 Ω. The differential voltage is detected by the receiver and converted back into a single-ended logic signal. When DIN is high (Logic 1), current flows out of the DOUT+ pin (current source) through RT and back into the DOUT− pin (current sink). At the receiver, this current develops a positive differential voltage across RT (with respect to the inverting input) and gives a Logic 1 at the receiver output. When DIN is low, DOUT+ sinks current and DOUT− sources current; a negative differential voltage across RT gives a Logic 0 at the receiver output. The output drive current is between ±2.5 mA and ±4.5 mA (typically ±3.1 mA), developing between ±250 mV and ±450 mV across a 100 Ω termination resistor. The received voltage is centered around the receiver offset of 1.2 V. In other words, the noninverting receiver input is typically (1.2 V + [310 mV/2]) = 1.355 V, and the inverting receiver input is (1.2 V − [310 mV/2]) = 1.045 V for Logic 1. For Logic 0, the inverting and noninverting output voltages are reversed. Note that because the differential voltage reverses polarity, the peak-to-peak voltage swing across RT is twice the differential voltage. Current-mode drivers offer considerable advantages over voltage-mode drivers such as RS-422 drivers. The operating current remains fairly constant with increased switching frequency, whereas that of voltage-mode drivers increases exponentially in most cases. This is caused by the overlap ADN4667 as internal gates switch between high and low, which causes currents to flow from the device power supply to ground. A current-mode device simply reverses a constant current between its two outputs, with no significant overlap currents. This is similar to emitter-coupled logic (ECL) and positive emitter-coupled logic (PECL), but without the high quiescent current of ECL and PECL. ENABLE INPUTS The ADN4667 has active high and active low enable inputs, which deactivate all the current drivers when in the disabled state. This also powers down the device and reduces the current consumption from typically 20 mA to typically 2.2 mA. A truth table for the enable inputs is shown in Table 5. Table 5. Enable Inputs Truth Table EN EN DIN DOUT+ DOUT− H L or open H L or open L ISINK H ISOURCE ISOURCE ISINK Any other combination of EN and EN X Inactive Inactive APPLICATIONS INFORMATION Figure 24 shows a typical application for point-to-point data transmission. 1/4 ADN4667 EN EN RECEIVER RT DIN 100Ω DOUT Figure 24. Typical Application Circuit Rev. 0 \| Page 11 of 12 11 Page

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