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PDF NJU8715 Data sheet ( Hoja de datos )

Número de pieza NJU8715
Descripción PWM/PDM / QFN28-N1
Fabricantes JRC 
Logotipo JRC Logotipo



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No Preview Available ! NJU8715 Hoja de datos, Descripción, Manual

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Switching Driver with Regulator
for Class-D Headphone Amplifier
NJU8715
PRELIMINARY
GENERAL DESCRIPTION
The NJU8715 is a switching driver with regulator for
class-D headphone amplifier. It incorporates an
optimum regulator for the driver of headphone amplifier,
class–D line amplifier and a beep amplifier. The
NJU8715 converts 1bit digital signal of the PWM or the
PDM to an analog signal output through a simple
external LC low-pass filter.
The NJU8715 provides a completed digital system
and high power-efficiency with class-D operation.
Therefore, it is suitable for portable audio applications.
PACKAGE OUTLINE
NJU8715KN1
FEATURES
2-channel 1bit Audio Signal Input
Headphone Output
Built-in Class D Line Amplifier
Built-in Regulator for Driver
Beep Function
Logic Operating Voltage
Regulator Operating Voltage
C-MOS Technology
1.9 to 2.6V (VDD)
4.0 to 5.75V (VG)
1.9 to 4.0V (VREG)
Package Outline
QFN28
PIN CONFIGURATION
28
1
MODEB
BEEPIN
DIN2
DIN1
OBEEP1
VSS
OUT1
CL
CH
VG
NC
OBEEP2
VSS
OUT2
BLOCK DIAGRAM
VDD
VSS
DIN1
MCK
DIN2
BEEPIN
Charge
Pump
Level Shifter
Level Shifter
Level Shifter
Level Shifter
Level Shifter
Control Logic
Regulator
Pre Driver
HP Amp
Pre Driver
LINE Amp
Pre Driver
HP Amp
Pre Driver
LINE Amp
BEEP Amp
BEEP Amp
VDDO1
OUT1
VSS
VDDO2
OUT2
VSS
OBEEP1
OBEEP2
Ver.2005-03-09
-1-

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NJU8715 pdf
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NJU3857515
(2)Power ON / Power DOWN Sequence(ENVG=L, VG: Externally applied)
< Power ON sequence >
1) Input the MCK after the start-up of VDD.
Apply VG after the start-up VDD.(As shown in the following sequence, VG increases to VDD through a
internal protection diode after VDD is turned on.)
2) Set ENREG at “H” level after the start-up of VG.
3) After setting ENREG at ”H” level, input audio signals(DIN1, DIN2).
4) Set EN1 at “H” level and EN2 at “L” level after audio signal input. The audio signal input must be
“Sound-less data” until VCONT reaches a steady state.
5) VCONT should be applied gradually to the target voltage. If the rising time of the application to the target
VCONT voltage is short, it may cause a pop-noise.
< Power DOWN sequence >
The sequence must be executed in inverse order of the power ON sequence.
VDD, VREG
ENVG
VG
ENREG
VCONT
100ms or more
100ms or more
EN1
EN2
MCK
DIN1, DIN2
Undefined
Data*
Sound-less
Data
Audio data
OUT1, OUT2 High impedance
Audio signal output
Sound-less Undefined
Data
Data*
High impedance
* : Do not set DIN1 and DIN2 at “H” level before the start-up of VDD.
Ver.2005-03-09
-5-

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NJU8715 arduino
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(2) VG: Externally applied (ENVG=L)
Regulator
Input
VG
MCK
DIN1
DIN2
BEEPIN
VREG
VSS
VSS
CFB
VREGO
VDDO1
VDDO2
VREF
CH
CL
VG
NJU3857515
OBEEP1
OUT1
47µH
220µF
OBEEP2
OUT2
47µH
220µF
16
Head Phone
16
Head Phone
VCONT
VREGO
Control Signal
VDD
VSS
VDD
Note.7) CH and CL pins must be opened when VG externally applied.
Note.8) De-coupling capacitors must be connected between each power supply pin and GND pin.
The capacitor value should be adjusted on the application circuit and the temperature. It may
malfunction if capacity value is small.
Note.9) A large-capacitance for the de-coupling capacitors for headphone speaker is recommended to improve a
low-frequency characteristics. In addition, a low-ESR(Equivalent series resistance) capacitor is
recommened for high power efficiency.
Note.10) The above circuit shows only application example and does not guarantee the any electrical
characteristics. Therefore, please consider and check the circuit carefully to fit your application.
Ver.2005-03-09
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 11 -

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