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PDF NJW1180A Data sheet ( Hoja de datos )
| Número de pieza | NJW1180A | |
| Descripción | Audio Processor | |
| Fabricantes | JRC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de NJW1180A (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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NJW1180A
Audio Processor with SRS WOW
s GENERAL DESCRIPTION
The NJW1180A is an audio processor with SRS WOW. It
includes all of functions processing audio signal for TV, such as
volume, balance, tone control and 4ch input selector. All of internal
status and variables are controlled by I2C BUS.
s FEATURES
q Operating Voltage
8 to 13 V
q SRS WOW (including SRS 3D, FOCUS and TruBass function)
q Simulated Stereo
q 4ch Input Selector
q Volume
0 to -80dB (0.5dB/step), MUTE
q Balance
0 to -30dB (1dB/step), MUTE
q Tone Control
-15dB to +15dB(1dB/step)
q I2C BUS Interface
q Bi-CMOS Technology
q Package Outline
QFP48-P1
s BLOCK DIAGRAM
s PACKAGE OUTLINE
NJW1180AFP1
IN1a
IN2a
IN3a
SEL
VOL1
Tone
IN4a
AGC
IN1b
IN2b
IN3b
IN4b
SEL
VOL1
Tone
WOW/Simulated
(FOCUS/TruBass/SRS 3D)
VOL2
VOL2
VOL2
Logic
Bias
CVO
CBA
CTH
CTL
CSR
CTB
CFCS
V+
GND
–1–
1 page  
www.DataSheet4U.com
NJW1180A
s I2C BUS CHARACTERISTICS (SDA, SCL)
I2C BUS Load Conditions: Pull up resistance 4k (Connected to +5V), Load capacitance 200pF (Connected to GND)
PARAMETER
SYM
BOL
STANDARD MODE
FAST MODE
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
Low Level Input Voltage
High Level Input Voltage
Hysteresis of Schmitt trigger inputs
LOW level output voltage (3mA at SDA pin)
Output fall time from VIHmin to VILmax with
a bus capacitance from 10pF to 400pF
Pulse width of spikes which must be suppressed by the input
filter
Input current each I/O pin with an input voltage between
0.1VDD and 0.9VDDmax
Capacitance for each I/O pin
SCL clock frequency
Hold time (repeated) START condition.
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START
condition
Capacitive load for each bus line
Noise margin at the LOW level
Noise margin at the HIGH level
VIL
VIH
Vhys
VOL
tof
tSP
Ii
Ci
fSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
tf
tSU:STO
tBUF
Cb
VnL
VnH
0.0
2.7
-
0
-
-
-10
-
-
4.0
4.7
4.0
4.7
0
250
-
-
4.0
4.7
-
0.5
1
- 1.5 0.0 - 1.5 V
- 5.0 2.7 - 5.0 V
- - 0.25 - - V
- 0.4 0
- 0.4 V
- 250 20
- 250 ns
+0.1Cb
- - 0 - 50 ns
- 10 -10 - 10 µA
- 10 -
- 10 pF
- 100 -
- 400 kHz
- - 0.6 - - µs
- - 1.3 - - µs
- - 0.6 - - µs
- - 0.6 - - µs
- 3.45 0
- 0.9 µs
- - 100 - - ns
- 1000 -
- 300 ns
- 300 -
- 300 ns
- - 0.6 - - µs
- - 1.3 - - µs
- 400 -
- 400 pF
- - 0.5 - - V
- -1- -V
Cb ; total capacitance of one bus line in pF.
SDA
tf
tr
SCL
tHD:STA
S
tLOW
tSU:DAT
tf
tHD:STA
tHD:DAT
tHIGH
tSU:STA
Sr
tSP tr
tBUF
tSU:STO
P
S
–5–
5 Page 
www.DataSheet4U.com
s Master Volume (Select Address: 00H)
Gain(dB)
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-21
-22
-23
-24
-25
-26
-27
-28
-29
-30
-31
-32
-33
-34
-35
-36
-37
-38
-39
-40
-41
-42
HEX
FF
FD
FB
F9
F7
F5
F3
F1
EF
ED
EB
E9
E7
E5
E3
E1
DF
DD
DB
D9
D7
D5
D3
D1
CF
CD
CB
C9
C7
C5
C3
C1
BF
BD
BB
B9
B7
B5
B3
B1
AF
AD
AB
D7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
D5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
VOL
D4 D3
11
11
11
11
10
10
10
10
01
01
01
01
00
00
00
00
11
11
11
11
10
10
10
10
01
01
01
01
00
00
00
00
11
11
11
11
10
10
10
10
01
01
01
NJW1180A
D2 D1 D0
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
– 11 –
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet NJW1180A.PDF ] | |
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