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PDF ADXL346 Data sheet ( Hoja de datos )
| Número de pieza | ADXL346 | |
| Descripción | Digital Accelerometer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
Three-Axis, ±2 g/±4 g/±8 g/±16g
Digital Accelerometer
ADXL346
www.daFtaEsAhTeeUt4RuE.cSom
Ultralow power: 25 µA to 145 µA at VS = 1.8 V (typ)
Power consumption scales automatically with bandwidth
User-selectable resolution
Fixed 10-bit resolution
Full resolution, where resolution increases with g range,
up to 13-bit resolution at ±16 g (maintaining 4 mg/LSB
scale factor in all g ranges)
32 levels of output data FIFO minimizes host processor load
Tap/double tap detection
Activity/inactivity monitoring
Free-fall detection
4- and 6-position orientation sensing
Supply and I/O voltage range: 1.7 V to 2.75 V
SPI (3 and 4 wire) and I2C digital interfaces
Flexible interrupt modes—any interrupt mappable to either
interrupt pin
Measurement ranges selectable via serial command
Bandwidth selectable via serial command
Wide temperature range (−40°C to +85°C)
10,000 g shock survival
Pb free/RoHS compliant
Small and thin: 3 mm × 3 mm × 1 mm LGA package
APPLICATIONS
Handsets
Gaming and pointing devices
Personal navigation devices
Hard disk drive (HDD) protection
Fitness equipment
Digital cameras
GENERAL DESCRIPTION
The ADXL346 is a small, thin, low power, three-axis accelerometer
with high resolution (13-bit) measurement at up to ±16 g. Digital
output data is formatted as 16-bit twos complement and is acces-
sible through either a SPI (3- or 4-wire) or I2C digital interface.
The ADXL346 is well suited for mobile device applications. It
measures the static acceleration of gravity in tilt-sensing appli-
cations, as well as dynamic acceleration resulting from motion
or shock. Its high resolution (4 mg/LSB) enables measurement
of inclination changes as little as 0.25°.
Several special sensing functions are provided. Activity and
inactivity sensing detect the presence or lack of motion and if
the acceleration on any axis exceeds a user-set level. Tap sensing
detects single and double taps. Free-fall sensing detects if the
device is falling. These functions can be mapped to one of two
interrupt output pins. An integrated 32-level first in, first out
(FIFO) buffer can be used to store data to minimize host
processor intervention. Both 4- and 6-position orientation
sensing are available for 2- and 3-D applications.
Low power modes enable intelligent motion-based power
management with threshold sensing and active acceleration
measurement at extremely low power dissipation.
The ADXL346 is supplied in a small, thin, 3 mm × 3 mm ×
1 mm, 16-lead, plastic package.
FUNCTIONAL BLOCK DIAGRAM
VS VDD I/O
AADDXXL3465
POWER
MANAGEMENT
3-AXIS
SENSOR
SENSE
ELECTRONICS
ADC
DIGITAL
FILTER
CONTROL
AND
INTERRUPT
LOGIC
INT1
INT2
32 LEVEL
FIFO
SERIAL I/O
SDA/SDI/SDIO
SDO/ALT
ADDRESS
SCL/SCLK
GND
CS
Figure 1.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
www.datasheet4u.com
VDD I/O
NC
NC
SCL/SCLK
GND
1 16 15 14 13
2 12
+x
3
+y +z
11
4 10
5 678 9
GND
GND
INT1
NC
INT2
ADXL346
Figure 2. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1 VDD I/O
2 NC
3 NC
4 SCL/SCLK
5 GND
6 SDA/SDI/SDIO
7 SDO/ALT ADDRESS
8 CS
9 INT2
10 NC
11 INT1
12 GND
13 GND
14 VS
15 Reserved
16 GND
Description
Digital Interface Supply Voltage.
Not Connected.
Not Connected.
Serial Communications Clock.
Must be connected to ground.
Serial Data (I2C)/Serial Data Input (SPI 4-Wire)/Serial Data Input and Output (SPI 3-Wire).
Serial Data Output/Alternate I2C Address Select.
Chip Select.
Interrupt 2 Output.
Not Connected.
Interrupt 1 Output.
Must be connected to ground.
Must be connected to ground.
Supply Voltage.
Reserved. This pin must be connected to VS.
Must be connected to ground.
Rev. PrA | Page 5 of 26
5 Page 
Preliminary Technical Data
SERIAL COMMUNICATIONS
I2C and SPI digital communications are available. In both cases,
the ADXL346 operates as a slave. I2C mode is enabled if the CS
pin is tied high to VDD I/O. The CS pin should always be tied high
www.datotaVshDeDeIt/O4uo.rcodmriven by an external controller, as there is no
default mode if the CS pin is left unconnected. This could
result in an inability to communicate with the part. In SPI
mode, the CS pin is controlled by the bus master. In both SPI
and I2C modes of operation, data transmitted from the
ADXL346 to the master device should be ignored during writes
to the ADXL346.
SPI
For SPI, either 3-wire or 4-wire configuration is possible, as
shown in the connection diagrams in Figure 21 and Figure 22.
Clearing the SPI bit in the DATA_FORMAT register (Address
0x31) selects 4-wire mode, whereas setting the SPI bit selects 3-wire
mode. The maximum SPI clock speed is 5 MHz with 12 pF
maximum loading, and the timing scheme follows clock
polarity (CPOL) = 1 and clock phase (CPHA) = 1.
ADDXXL334465
CS
SDA/SDI/SDIO
SDO
SCL/SCLK
PROCESSOR
D OUT
D IN/OUT
D IN
D OUT
Figure 21. 4-Wire SPI Connection
AADDXXL334465
CS
SDA/SDI/SDIO
SDO
SCL/SCLK
PROCESSOR
D OUT
D IN/OUT
D OUT
Figure 22. 3-Wire SPI Connection
CS is the serial port enable line and is controlled by the SPI
master. It must go low at the start of a transmission and back
high at the end of a transmission as shown in Figure 23. SCLK
is the serial port clock and is supplied by the SPI master. It is
stopped high when CS is high during a period of no
ADXL346
transmission. SDI and SDO are the serial data input and output,
respectively. Data should be sampled at the rising edge of SCLK.
To read or write multiple bytes in a single transmission, the
multibyte bit, located after the R/W bit in the first byte transfer
(MB in Figure 23 to Figure 25), must be set. After the register
addressing and the first byte of data, each subsequent set of
clock pulses (eight clock pulses) causes the ADXL346 to point
to the next register for a read or write. This shifting continues
until the clock pulses are ceased and CS is deasserted. To perform
reads or writes on different, nonsequential registers, CS must be
deasserted between transmissions and the new register must be
addressed separately.
The timing diagram for 3-wire SPI reads or writes is shown in
Figure 23. The 4-wire equivalents for SPI reads and writes are
shown in Figure 24 and Figure 25, respectively.
Table 8. SPI Timing Specifications
(TA = 25°C, VS = 1.8 V, VDD I/O = 1.8 V)
Parameter Limit
Unit
Description
fSCLK
5
MHz max SPI clock frequency
tSCLK
200
ns min
1/(SPI clock frequency)
mark/space ratio for the
SCLK input is 40/60 to
60/40
tDELAY
200
ns min
CS Falling edge to
SCLK falling edge
tQUIET
200
ns min
SCLK rising edge to
CS rising edge
tS
0.4 × tSCLK ns min
SCLK low pulse width
(space)
tM
0.4 × tSCLK ns min
SCLK high pulse width
(mark)
tSDO 8
ns max
SCLK falling edge to SDO
transition
tSETUP
10
ns min
SDI valid before SCLK
rising edge
tHOLD
10
ns min
SDI valid after SCLK
rising edge
Rev. PrA | Page 11 of 26
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet ADXL346.PDF ] | |
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