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PDF ADIS16405 Data sheet ( Hoja de datos )
| Número de pieza | ADIS16405 | |
| Descripción | High Precision Tri-Axis Sensor | |
| Fabricantes | Analog Devices | |
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Tri-axis, digital gyroscope with digital range scaling
±75°/sec, ±150°/sec, ±300°/sec settings
Tri-axis, ±18 g digital accelerometer
Tri-axis, ±2.5 gauss digital magnetometer
220 ms start-up time
Factory-calibrated sensitivity, bias, and axial alignment
Calibration temperature range: −40°C to +85°C
Digitally controlled bias calibration
Digitally controlled sample rate, up to 819.2 SPS
External clock input enables sample rates up to 1200 SPS
Digitally controlled filtering
Programmable condition monitoring
Auxiliary digital input/output
Digitally activated self-test
Programmable power management
Embedded temperature sensor
SPI-compatible serial interface
Auxiliary, 12-bit ADC input and DAC output
Single-supply operation: 4.75 V to 5.25 V
2000 g shock survivability
Operating temperature range: −40°C to +105°C
APPLICATIONS
Unmanned aerial vehicles
Platform control
Digital compassing
Navigation
GENERAL DESCRIPTION
The ADIS16405 iSensor® is a complete inertial system that includes
a tri-axis gyroscope, a tri-axis accelerometer, and a tri-axis mag-
netometer. The ADIS16405 combines industry-leading iMEMS®
technology with signal conditioning that optimizes dynamic
performance. The factory calibration characterizes each sensor
for sensitivity, bias, alignment, and linear acceleration (gyroscope
bias). As a result, each sensor has its own dynamic compensation
for correction formulas that provide accurate sensor measurements
over a temperature range of −40°C to +85°C. The magnetometers
employ a self-correction function to provide accurate bias
performance over temperature as well.
The ADIS16405 provides a simple, cost-effective method for
integrating accurate, multi-axis inertial sensing into industrial
systems, especially when compared with the complexity and
investment associated with discrete designs.
Tri-Axis Inertial Sensor
with Magnetometer
ADIS16405
FUNCTIONAL BLOCK DIAGRAM
AUX_
ADC
AUX_
DAC
TEMPERATURE
SENSOR
TRI-AXIS MEMS
ANGULAR RATE
SENSOR
SIGNAL
CONDITIONING
AND
CONVERSION
CALIBRATION
AND
DIGITAL
PROCESSING
OUTPUT
REGISTERS
AND SPI
INTERFACE
TRI-AXIS MEMS
ACCELERATION
SENSOR
CS
SCLK
DIN
DOUT
TRI-AXIS
MAGNETIC
SENSOR
ALARMS
POWER
MANAGEMENT
SELF-TEST
ADIS16405
DIGITAL
CONTROL
RST DIO1 DIO2 DIO3 DIO4/
CLKIN
Figure 1.
VCC
GND
All necessary motion testing and calibration are part of the produc-
tion process at the factory, greatly reducing system integration time.
Tight orthogonal alignment simplifies inertial frame alignment
in navigation systems. An improved SPI interface and register
structure provide faster data collection and configuration control.
By using a compatible pinout and the same package as the
ADIS1635x and ADIS1636x families, upgrading to the ADIS16405
requires only firmware changes to accommodate additional sensors
and register map updates.
This compact module is approximately 23 mm × 23 mm × 23 mm
and provides a flexible connector interface, which enables multiple
mounting orientation options.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
ADIS16405
TIMING SPECIFICATIONS
TA = 25°C, VCC = 5 V, unless otherwise noted.
Table 2.
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Parameter Description
fSCLK
tSTALL
Stall period between data
tREADRATE
Read rate
tCS Chip select to clock edge
tDAV DOUT valid after SCLK edge
tDSU DIN setup time before SCLK rising edge
tDHD DIN hold time after SCLK rising edge
tSCLKR, tSCLKF SCLK rise/fall times
tDF, tDR
DOUT rise/fall times
tSFS CS high after SCLK edge
t1 Input sync pulse width
t2 Input sync to data ready output
t3 Input sync period
Normal Mode
(SMPL_PRD ≤ 0x09)
Min1 Typ Max
0.01 2.0
9
40
48.8
100
24.4
48.8
5 12.5
5 12.5
5
5
600
833
1Guaranteed by design and characterization, but not tested in production.
Low Power Mode
(SMPL_PRD ≥ 0x0A)
Min1 Typ Max
0.01 0.3
75
150
48.8
100
24.4
48.8
5 12.5
5 12.5
5
Burst Mode
Min1 Typ Max
0.01 1.0
1/fSCLK
48.8
24.4
48.8
5
5
5
100
12.5
12.5
Unit
MHz
μs
μs
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
TIMING DIAGRAMS
CS
SCLK
tCS
1
DOUT
MSB
DIN W/R
23 4 56
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A6 A5 A4 A3 A2
Figure 2. SPI Timing and Sequence
tREADRATE
tSTALL
CS
15 16
tSFS
DB2
DB1
LSB
D2 D1 LSB
SCLK
SYNC
CLOCK (DIO4)
DATA
READY
Figure 3. Stall Time and Data Rate
t3
t2
t1
Figure 4. Input Clock Timing Diagram
Rev. 0 | Page 5 of 16
5 Page 
ADIS16405
CS 1 2 3 4 5
13
SCLK
DIN
www.datasheet4u.com
DOUT
0x3E00
PREVIOUS
DON’T CARE
SUPPLY_OUT
XGYRO_OUT
YGYRO_OUT
ZGYRO_OUT
AUX_ADC
Figure 12. Burst Mode Read Sequence
OUTPUT DATA REGISTERS
Figure 6 provides the positive measurement direction for each
gyroscope, accelerometer, and magnetometer. Table 9 provides
the configuration and scale factor for each output data register
in the ADIS16405. All inertial sensor outputs are 14 bits in length
and are in twos complement format, which means that 0x0000
is equal to 0 LSB, 0x0001 is equal to +1 LSB, and 0x3FFF is equal
to −1 LSB. The following is an example of how to calculate the
sensor measurement from the XGYRO_OUT:
XGYRO_OUT = 0x3B4A
0x000 – 0x3B4A = −0x04B6 = (4 × 256 + 11 × 16 +6) −
0x04B6 = −1206 LSB
ND EA
MSB FOR 14-BIT OUTPUT
MSB FOR 12-BIT OUTPUT
Figure 13. Output Register Bit Assignments
Auxiliary ADC
The AUX_ADC register provides access to the auxiliary ADC
input channel. The ADC is a 12-bit successive approximation
converter that has an equivalent input circuit to the one shown
in Figure 14. The maximum input is 3.3 V. The ESD protection
diodes can handle 10 mA without causing irreversible damage.
The on resistance (R1) of the switch has a typical value of 100 Ω.
The sampling capacitor, C2, has a typical value of 16 pF.
VCC
Rate = 0.05°/sec × (−1206) = −60.3°/sec
Therefore, an XGYRO_OUT output of 0x3B4A corresponds to
a clockwise rotation about the z-axis (see Figure 6) of 60.3°/sec
when looking at the top of the package.
Table 9. Output Data Register Formats
D R1 C2
C1 D
Figure 14. Equivalent Analog Input Circuit
(Conversion Phase: Switch Open, Track Phase: Switch Closed)
Register
SUPPLY_OUT
XGYRO_OUT1
YGYRO_OUT1
ZGYRO_OUT1
XACCL_OUT
YACCL_OUT
ZACCL_OUT
XMAGN_OUT
YMAGN_OUT
ZMAGN_OUT
TEMP_OUT2
AUX_ADC
Bits Format
14 Binary, 5 V = 0x0814
14 Twos complement
14 Twos complement
14 Twos complement
14 Twos complement
14 Twos complement
14 Twos complement
14 Twos complement
14 Twos complement
14 Twos complement
12 Twos complement
12 Binary, 1 V = 0x04D9
Scale
2.42 mV
0.05°/sec
0.05°/sec
0.05°/sec
10 mg
10 mg
10 mg
0.5 mgauss
0.5 mgauss
0.5 mgauss
0.14°C
0.81 mV
1 Assumes that the scaling is set to ±300°/sec. This factor scales with the range.
2 The typical output for this register at +25°C is 0x0000.
CALIBRATION
Manual Bias Calibration
The bias offset registers in Table 10, Table 11, and Table 12
(hard-iron correction for magnetometer) provide a manual
adjustment function for the output of each sensor. For example,
if XGYRO_OFF equals 0x1FF6, the XGYRO_OUT offset shifts
by −10 LSB, or −0.125°/sec. The DIN command for the upper
byte is DIN = 0x9B1F; for the lower byte, DIN = 0x9AF6.
Table 10. XGYRO_OFF, YGYRO_OFF, ZGYRO_OFF
Bits Description
[15:13]
Not used.
[12:0]
Data bits. Twos complement, 0.0125°/sec per LSB.
Typical adjustment range = ±50°/sec.
Table 11. XACCL_OFF, YACCL_OFF, ZACCL_OFF
Each output data register uses the bit assignments shown in
Figure 13. The ND flag indicates that unread data resides in the
output data registers. This flag clears and returns to 0 during an
output register read sequence. It returns to 1 after the next internal
sample updates the registers with new data. The EA flag indicates
that one of the error flags in the DIAG_STAT register (see Table 23)
is active (true). The remaining 14 bits are for data.
Bits
[15:12]
[11:0]
Description
Not used.
Data bits. Twos complement, 3.3 mg/LSB.
Typical adjustment range = ±6.75 g.
Table 12. XMAGN_HIF, YMAGN_HIF, ZMAGN_HIF
Bits Description
[15:14]
Not used.
[13:0]
Data bits. Twos complement, 0.5 mgauss/LSB.
Typical adjustment range = ±4 gauss.
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADIS16405.PDF ] | |
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