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PDF NL6448AC33-10 Data sheet ( Hoja de datos )
| Número de pieza | NL6448AC33-10 | |
| Descripción | TFT Clolr LCD Module | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
TFT COLOR LCD MODULE
NL6448AC33-10
26 cm (10.4 type), 640 × 480 pixels 4096 colors,
incorporated one lamp/edge-light type backlight
DESCRIPTION
NL6448AC33-10 is a TFT (thin film transistor) active matrix color liquid crystal display (LCD) module comprising
amorphous silicon TFT attached to each signal electrode, a driving circuit, and a backlight.
The 26 cm diagonal display area contains 640 × 480 pixels and can display 4096 colors simultaneously.
By utilizing one lamp/edge-light type backlight, a very thin profile design and low power consumption have
been achieved.
FEATURES
™ High contrast ratio, wide color gamut
™ High-speed response
™ Incorporated edge light type backlight and Inverter
™ Data enable function
APPLICATIONS
™ Notebook personal computer (PC), word processor
™ Display terminals for control system
™ New media
™ Control board for NC machine
™ Monitors for process controller
Document No. EN0094EJ2V1DS00 (2nd edition)
(NC-1011)
Date Published May 1996 M
Printed in Japan
© 1995
1 page  
NL6448AC33-10
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<side view>
Upper side
11
Display side CN5
55
<rear view>
Lower side
<side view>
11
CN1
10 10
11 11
CN2
23 23
24 24
CN3
34 34
1
2
CN4
1
2
Display side
(3) PIN DESCRIPTION
Symbol
R0 – R3
G0 – G3
B0 – B3
Function
Display data
Hsync
Vsync
Horizontal sync.
Vertical sync.
CLK Dot clock
DE Data enable
MODE
Timing mode select
VCCOFFO VCC ON / OFF signal
ACA
BLOFFO
BRTH
BRTL
VCC
VDD
GND
GNDB
Brightness mode select
Backlight ON/OFF signal
Backlight brightness control
+5.0 V (±5 %)
+5.2 V to + 20.0 V
Logic ground
Backlight ground
Description
4-bit digital signals for each of RGB primary colors.
Horizontal synchronous signal.
Vertical synchronous signal.
Timing signal for display data. Module strobes the display data at the
falling edge of CLK.
The signal that defines the graphic data that is to be displayed on the
screen.
When MODE = L, the function of this pin is ignored. (Keep DE high or low)
When MODE = H, the period of DE = H is the display period of the module.
MODE = H : DE mode (data enable function is active)
MODE = L : fixed timing mode (data enable function is ignored)
VCCOFFO = H : Power on inside of the module.
VCCOFFO = L : Power off inside of the module.
ACA = H : battery mode (low luminance)
ACA = L : AC ada[ter mode (high luminance)
BLOFFO = H : backlight on
BLOFFO = L : backlight off
Connect a variable resistor (10 kΩ±5 %, B curve)
between BRTH and BRTL.
Power supply for logic and LCD driving.
Power supply for backlight
Ground for VCC
Ground for backlight
GND is not connected to the module frame.
GNDB is not connected to the module frame.
GNDB is separated from GND in the module.
5
5 Page 
NL6448AC33-10
(2) Definition of input signal timing (DE mode) Note
<Horizontal>
Horizontal display period (Thd)
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DE
Hsync
Horizontal back-porch (Thb)
Horizontal front-porch (Thf)
Horizontal synchronous pulse width (Thp)
Horizontal period (Th)
<Vertical>
DE
Vsync
Vertical display period (Tvd)
Vertical back-porch (Tvb)
Vertical front-porch (Tvf)
Vertical synchronous pulse width (Tvp)
Vertical period (Tv)
Note 1 : Regarding how ro count H/CLK, refer to the input signal
timing chart (DE mode).
CLK
VI H
1.5 V
VI L
R0 - R3
G0 - G3
B0 - B3
Tc
Tch
Tc = 39.722 ns
Tch = 15.9 ns (min.)
Tcrf = 10 ns (max.)
Tch = Tc = 0.4 to 0.6
Tcrf
Tds Tdh
Thch
Tes
Tdrf
Thcs
VI H
1.5 V
VI L
Tds = 8 ns (min.)
Tdh = 12 ns (min.)
Tdrf = 10 ns (max.)
Thch = 12 ns (min.)
Teh Thcs = 8 ns (min.)
VI H
DE 1.5 V
VI L
Hsync
Terf
VI H
1.5 V
VI L
Thrf
Thrf = 10 ns (max.)
Vsync
VI H
1.5 V
VI L
Hsync 1.5 V
Tvh
Tvrf
Tvs
1.5 V
Tvrf = 10 ns (max.)
Tvh = 15 ns (min.)
Tvs = 15 ns (min.)
11
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet NL6448AC33-10.PDF ] | |
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