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PDF LTC6802-1 Data sheet ( Hoja de datos )
| Número de pieza | LTC6802-1 | |
| Descripción | Multicell Battery Stack Monitor | |
| Fabricantes | Linear Technology | |
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FEATURES
www.datasheet4u.com
n Measures up to 12 Li-Ion Cells in Series (60V Max)
n Stackable Architecture Enables >1000V Systems
n 0.25% Maximum Total Measurement Error
n 13ms to Measure All Cells in a System
n Cell Balancing:
On-Chip Passive Cell Balancing Switches
Provision for Off-Chip Passive Balancing
n Two Thermistor Inputs Plus On-board
Temperature Sensor
n 1MHz Serial Interface with Packet Error Checking
n High EMI Immunity
n Delta Sigma Converter With Built In Noise Filter
n Open Wire Connection Fault Detection
n Low Power Modes
n 44-Lead SSOP Package
APPLICATIONS
n Electric and Hybrid Electric Vehicles
n High Power Portable Equipment
n Backup Battery Systems
n High Voltage Data Acquisition Systems
Electrical Specifications Subject to Change
LTC6802-1
Multicell
Battery Stack Monitor
DESCRIPTION
The LTC®6802-1 is a complete battery monitoring IC that
includes a 12-bit ADC, a precision voltage reference, a
high voltage input multiplexer and a serial interface. Each
LTC6802-1 can measure up to 12 series connected battery
cells with an input common mode voltage up to 60V. Using
a unique level-shifting serial interface, multiple LTC6802-1
devices can be connected in series, without optocouplers
or isolators, allowing for monitoring of every cell in a long
string of series-connected batteries.
When multiple LTC6802-1 devices are connected in series
they can operate simultaneously, permitting all cell voltages
in the stack to be measured within 13ms.
To minimize power, the LTC6802-1 offers a measure mode
to monitor each cell for overvoltage and undervoltage
conditions. A standby mode is also provided.
Each cell input has an associated MOSFET switch for
discharging overcharged cells.
The related LTC6802-2 offers an individually addressable
serial interface.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
NEXT 12-CELL
PACK ABOVE
Typical Application
V+
LTC6802-1
SERIAL DATA
TO LTC6802-1
DIE TEMP
ABOVE
12-CELL
BATTERY
STRING
REGISTERS
AND
CONTROL
MUX
12-BIT
Δ∑ ADC
NEXT 12-CELL
PACK BELOW
V–
100k NTC
EXTERNAL
TEMP
10ppm VOLTAGE
REFERENCE
SERIAL DATA
TO LTC6802-1
BELOW
68021 TA01a
100k
Measurement Error Over
Extended Temperature
0.30
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–50
–25
0 25 50 75 100 125
TEMPERATURE (°C)
68021p
1
1 page  
LTC6802-1
PIN FUNCTIONS
CSBO (Pin 1): Chip Select Output (Active Low). CSBO is
a buffered version of the chip select input, CSBI. CSBO
wwwd.draivtaesshetehte4un.ceoxmt IC in the daisy chain. See Serial Port in the
Applications Information section.
SDOI (Pin 2): Serial Data I/O Pin. SDOI transfers data to
and from the next IC in the daisy chain. See Serial Port in
the Applications Information section.
SCKO (Pin 3): Serial Clock Output. SCKO is a buffered ver-
sion of SCKI. SCKO drives the next IC in the daisy chain.
See Serial Port in the Applications Information section.
V+ (Pin 4): Tie pin 4 to the most positive potential in the
battery stack. Typically V+ is the same potential as C12.
C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1 (Pins
5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27): C1 through
C12 are the inputs for monitoring battery cell voltages.
Up to 12 cells can be monitored. The lowest potential is
tied to pin V–. The next lowest potential is tied to C1 and
so forth. See the figures in the Applications Information
section for more details on connecting batteries to the
LTC6802-1.
The LTC6802-1 can monitor a series connection of up to
12 cells. The LTC6802-1 cannot monitor parallel combina-
tions of series cells. For example, 3 parallel groups of 4
series cells are not allowed.
S12, S11, S10, S9, S8, S7, S6, S5, S4, S3, S2, S1 (Pins
6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28): S1 though
S12 pins are used to balance battery cells. If one cell in a
series becomes over charged, an S output can be used to
discharge the cell. Each S output has an internal N-channel
MOSFET for discharging. See the Block Diagram. The NMOS
has a maximum on resistance of 20Ω. An external resistor
should be connected in series with the NMOS to dissipate
heat outside of the LTC6802-1 package. When using the
internal MOSFETs to discharge cells, the die temperature
should be monitored. See Power Dissipation and Thermal
Shutdown in the Applications Information section.
The S pins also feature an internal 10k pull-up resistor. This
allows the S pins to be used to drive the gates of external
MOSFETs for higher discharge capability.
V– (Pin 29): Connect V– to the most negative potential in
the series of cells.
NC (Pin 30): Pin 30 is internally connected to V– through
10Ω. Pin 30 can be left unconnected or connected to pin
29 on the PCB.
VTEMP1, VTEMP2 (Pins 31, 32): Temperature Sensor Inputs.
The ADC measures the voltage on VTEMPx with respect to
V– and stores the result in the TMP registers. The ADC
measurementsarerelativetotheVREF pinvoltage.Therefore
a simple thermistor and resistor combination connected
to the VREF pin can be used to monitor temperature. The
VTEMP inputs can also be general purpose ADC inputs.
Any voltage from 0V to 5.125V referenced to V– can be
measured.
VREF (Pin 33): 3.075V Voltage Reference Output. This pin
should be bypassed with a 1μF capacitor. The VREF pin can
drive a 100k resistive load connected to V–. Larger loads
should be buffered with an LT6003 op amp, or similar
device.
VREG (Pin 34): Linear Voltage Regulator Output. This pin
should be bypassed with a 1μF capacitor. The VREG pin is
capable of supplying up to 4mA to an external load. The
VREG pin does not sink current.
TOS (Pin 35): Top of Stack Input. Tie TOS to VREG when
the LTC6802-1 is the top device in a daisy chain. Tie TOS
to V– when the LTC6802-1 is any other device in a daisy
chain. When TOS is tied to VREG, the LTC6802-1 ignores
the SDOI input. When TOS is tied to V–, the LTC6802-1
expects data to be passed to and from the SDOI pin.
MMB (Pin 36): Monitor Mode (Active Low) Input. When
MMB is low (same potential as V–), the LTC6802-1 goes
into monitor mode. See Modes of Operation in the Ap-
plications Information section.
WDTB (Pin 37): Watchdog Timer Output (Active Low).
If there is no activity on the SCKI pin for 2 seconds, the
WDTB output is asserted. The WDTB pin is an open drain
NMOS output. When asserted it pulls the output down to
V– and resets the configuration register to its default state.
The watchdog timer function can be disabled by setting
WDTEN = 0 in the configuration register. See Watchdog
Timer Circuit in the Applications Information section.
68021p
5
5 Page 
LTC6802-1
OPERATION
identical codes. For Self Test 1 the registers will contain
0x555. For Self Test 2, the registers will contain 0xAAA.
wwwT.dhaetastihmeeet4rue.cqoumired for the self test function is the same as
required to measure all cell voltages or all temperature
sensors. Perform the self test function with CDC[2:0] set
to 1 in the configuration register.
USING THE S PINS AS DIGITAL OUTPUTS OR
GATE DRIVERS
The S outputs include an internal 10k pull-up resistor.
Therefore the S pins will behave as a digital output when
loaded with a high impedance, e.g. the gate of an external
MOSFET. For applications requiring high battery discharge
currents, connect a discrete PMOS switch device and suit-
able discharge resistor to the cell, and the gate terminal
to the S output pin, as illustrated in Figure 4.
SI2351DS
C(n)
15Ω
1W
VISHAY CRCW2512 SERIES
S(n)
C(n – 1)
68021 F04
Figure 4. External Discharge FET Connection (One Cell Shown)
POWER DISSIPATION AND THERMAL SHUTDOWN
The MOSFETs connected to the pins S1 through S12 can be
used to discharge battery cells. An external resistor should
be used to limit the power dissipated by the MOSFETs. The
maximum power dissipation in the MOSFETs is limited by
the amount of heat that can be tolerated by the LTC6802-1.
Excessive heat results in elevated die temperatures. The
electrical characteristics are guaranteed for die tempera-
tures up to 85°C. Little or no degradation will be observed
in the measurement accuracy for die temperatures up
to 105°C. Damage may occur near 150°C, therefore the
recommended maximum die temperature is 125°C.
To protect the LTC6802-1 from damage due to overheating,
a thermal shutdown circuit is included. Overheating of the
device can occur when dissipating significant power in the
cell discharge switches or when communicating frequently
to the device using the current-mode serial interface. The
problem is exacerbated when operating with a large volt-
age between V+ and V– or when the thermal conductivity
of the system is poor.
The thermal shutdown circuit is enabled whenever the
device is not in standby mode (see Modes of Operation).
For the LTC6802-1, the thermal shutdown circuit will also
be enabled when any current mode input or output is
sinking or sourcing current. If the temperature detected
on the device goes above approximately 145°C, the con-
figuration registers will be reset to default states, turning
off all discharge switches and disabling A/D conversions.
Also, for the LTC6802-1, the current mode interface will
not operate until the overtemperature condition goes away.
When a thermal shutdown has occurred, the THSD bit
in the temperature register group will go high. The bit is
cleared by performing a read of the temperature registers
(RDTMP command).
Since thermal shutdown interrupts normal operation, the
internal temperature monitor should be used to determine
when the device temperature is approaching unacceptable
levels.
APPLICATIONS INFORMATION
USING THE LTC6802-1 WITH LESS THAN 12 CELLS
The LTC6802-1 can be used with as few as four cells.
The minimum number of cells is governed by the supply
voltage requirements of the LTC6802-1. The sum of the
cell voltages must be 10V to guarantee that all electrical
specifications are met.
Figure 5 shows an example of the LTC6802-1 when used
to monitor seven cells. The lowest C inputs connect to the
seven cells and the upper C inputs connect to V+. Other
configurations, e.g. 9 cells, would be configured in the
same way: the lowest C inputs connected to the battery
cells and the unused C inputs connected to V+. The unused
inputs will result in a reading of 0V for those channels.
68021p
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC6802-1.PDF ] | |
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