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PDF ADP3419 Data sheet ( Hoja de datos )
| Número de pieza | ADP3419 | |
| Descripción | High Voltage MOSFET Driver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADP3419 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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Dual Bootstrapped, High Voltage MOSFET
Driver with Output Disable
ADP3419
www.daFtaEsAheTeUt4Ru.EcSom
All-in-one synchronous buck driver
One PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable function
Crowbar control
Synchronous override control
Undervoltage lockout
APPLICATIONS
Mobile computing CPU core power converters
Multiphase desk-note CPU supplies
Single-supply synchronous buck converters
Nonsynchronous-to-synchronous drive conversion
GENERAL DESCRIPTION
The ADP3419 is a dual MOSFET driver optimized for driving
two N-channel switching MOSFETs in nonisolated synchro-
nous buck power converters used to power CPUs in portable
computers. The driver impedances have been chosen to provide
optimum performance in multiphase regulators at up to 25 A
per phase. The high-side driver can be bootstrapped relative to
the switch node of the buck converter and is designed to
accommodate the high voltage slew rate associated with floating
high-side gate drivers.
The ADP3419 includes an anticross-conduction protection
circuit, undervoltage lockout to hold the switches off until the
driver has sufficient voltage for proper operation, a crowbar
input that turns on the low-side MOSFET independently of the
input signal state, and a low-side MOSFET disable pin to
provide higher efficiency at light loads. The SD pin shuts off
both the high-side and the low-side MOSFETs to prevent rapid
output capacitor discharge during system shutdown.
The ADP3419 is specified over the extended commercial
temperature range of 0°C to 100°C and is available in a 10-lead
MSOP package.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
VCC
5
BST
10
IN 1
SD 2
DRVLSD 3
CROWBAR 4
UVLO,
OVERLAP
PROTECTION,
SHUTDOWN
AND
CROWBAR
CIRCUITS
ADP3419
7
GND
Figure 1.
9 DRVH
8 SW
6 DRVL
GENERAL APPLICATION CIRCUIT
5V VDC
FROM CONTROLLER
PWM OUTPUT
FROM SYSTEM
ENABLE CONTROL
FROM
CONTROLLER
FROM CONTROLLER
CLAMP OUTPUT
5
VCC
1 IN
BST 10
ADP3419
2 SD
DRVH 9
3 DRVLSD
SW 8
4 CROWBAR DRVL 6
GND
7
Figure 2.
VOUT
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
www.daVtCasCheet4u.com
BST
BST to SW
SW
DRVH
DRVL
All Other Inputs and Outputs
θJA
2-Layer Board
4-Layer Board
Operating Ambient Temperature
Range
Junction Temperature Range
Storage Temperature Range
Lead Temperature Range
Soldering (10 s)
Vapor Phase (60 s)
Infrared (15 s)
Rating
−0.3 V to +7 V
−0.3 V to +30 V
−0.3 V to +7 V
−3 V to +25 V
SW − 0.3 V to BST + 0.3 V
−0.3 V to VCC + 0.3 V
−0.3 V to VCC + 0.3 V
340°C/W
220°C/W
0°C to 100°C
0°C to 150°C
−65°C to +150°C
300°C
215°C
220°C
ADP3419
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Unless otherwise specified, all voltages are referenced to GND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 16
5 Page 
ADP3419
APPLICATION INFORMATION
SUPPLY CAPACITOR SELECTION
For the supply input (VCC) of the ADP3419, a local bypass
capacitor is recommended to reduce the noise and to supply
www.dastoamsheeoeft4tuh.ecopmeak currents drawn. Use a 10 µF or 4.7 µF
multilayer ceramic (MLC) capacitor. MLC capacitors provide
the best combination of low ESR and small size, and can be
obtained from the following vendors.
Table 5.
Vendor
Murata
Taiyo-Yuden
Tokin
Part Number
GRM235Y5V106Z16
EMK325F106ZF
C23Y5V1C106ZP
Web Address
www.murata.com
www.t-yuden.com
www.tokin.com
Keep the ceramic capacitor as close as possible to the ADP3419.
BOOTSTRAP CIRCUIT
The bootstrap circuit uses a charge storage capacitor (CBST) and
a Schottky diode (D1), as shown in Figure 17. Selection of these
components can be done after the high-side MOSFET has been
chosen. The bootstrap capacitor must have a voltage rating that
is able to handle at least 5 V more than the maximum supply
voltage. The capacitance is determined by
C BST
= Q HSGATE
∆VBST
(1)
where:
QHSGATE is the total gate charge of the high-side MOSFET.
∆VBST is the voltage droop allowed on the high-side MOSFET
drive.
For example, two IRF7811 MOSFETs in parallel have a total
gate charge of about 36 nC. For an allowed droop of 100 mV,
the required bootstrap capacitance is 360 nF. A good quality
ceramic capacitor should be used, and derating for the signifi-
cant capacitance drop of MLCs at high temperature must be
applied. In this example, selection of 470 nF or even 1 µF would
be recommended.
A Schottky diode is recommended for the bootstrap diode due
to its low forward drop, which maximizes the drive available for
the high-side MOSFET. The bootstrap diode must also be able
to handle at least 5 V more than the maximum battery voltage.
The average forward current can be estimated by
IF(AVG) = QHSGATE × fMAX
(2)
where fMAX is the maximum switching frequency of the
controller.
POWER AND THERMAL CONSIDERATIONS
The major power consumption of the ADP3419-based driver
circuit is from the dissipation of MOSFET gate charge. It can be
estimated as
PMAX ≈ VCC × (QHSGATE + QLSGATE )× f MAX
(3)
where:
VCC is the supply voltage 5 V.
fMAX is the highest switching frequency.
QHSGATE and QLSGATE are the total gate charge of high-side and
low-side MOSFETs, respectively.
For example, the ADP3419 drives two IRF7821 high-side
MOSFETs and two IRF7832 low-side MOSFETs. According to
the MOSFET data sheets, QHSGATE = 18.6 nC and QLSGATE =
68 nC. Given that fMAX is 300 kHz, PMAX would be about
130 mW.
Part of this power consumption generates heat inside the
ADP3419. The temperature rise of the ADP3419 against its
environment is estimated as
∆T ≈ θ JA × PMAX × η
(4)
where θJA is ADP3419’s thermal resistance from junction to air,
given in the absolute maximum ratings as 220°C/W for a
4-layer board.
The total MOSFET drive power dissipates in the output
resistance of ADP3419 and in the MOSFET gate resistance as
well. η represents the ratio of power dissipation inside the
ADP3419 over the total MOSFET gate driving power. For
normal applications, a rough estimation for η is 0.7. A more
accurate estimation can be calculated using
η
≈
QHSGATE
QHSGATE + QLSGATE
× ⎜⎛
⎝
0.5 × R1
R1 + RHSGATE
+R
+
0.5 × R2
R2 + RHSGATE
⎟⎞
⎠
+ QLSGATE
QHSGATE + QLSGATE
×
⎜⎛
⎝
0.5 × R3
R3 + RLSGATE
+
0.5 × R4
R4 + RLSGATE
⎟⎞
⎠
(5)
where:
R1 and R2 are the output resistances of the high-side driver:
R1 = 1.7 (DRVH − BST), R2 = 0.8 (DRVH − SW).
R3 and R4 are the output resistances of the low-side driver:
R3 = 1.7 (DRVL − VCC), R4 = 0.8 (DRVL − GND).
R is the external resistor between the BST pin and the BST
capacitor.
RHSGATE and RLSGATE are gate resistances of high-side and low-side
MOSFETs, respectively.
Assuming that R = 0 and that RHSGATE = RLSGATE = 0.5, Equation 5
gives a value of η = 0.71. Based on Equation 4, the estimated
temperature rise in this example is about 22°C.
Rev. A | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADP3419.PDF ] | |
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