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PDF LE28FV4001T Data sheet ( Hoja de datos )
| Número de pieza | LE28FV4001T | |
| Descripción | 4MEG (52488 x 8 Bits) Flash Memory | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number : EN*5468
CMOS LSI
LE28FV4001M, T, R-20/25
4MEG (52488 × 8 Bits) Flash Memory
Preliminary
Overview
The LE28FV4001M, T, R Series are 4 MEG flash
memory products that feature a 542488-word × 8-bit
organization and 3.3 V single-voltage power supply
operation. CMOS peripheral circuits were adopted for
high speed, low power, and ease of use. The
LE28FV4001M also supports high-speed data rewriting
by providing a sector (256 bytes) erase function.
Package Dimensions
unit: mm
3205-SOP32
[LE28FV4001M. T, R]
Features
• Highly reliable 2 layer polysilicon CMOS flash
EEPROM process
• Read and write operations using a 3.3 V single-voltage
power supply
• High-speed access: 200 and 250 ns
• Low power
— Operating (read): 10 mA (maximum)
— Standby: 20 µA (maximum)
• Highly reliable read write
—Number of sector write cycles: 104 cycles
— Data retention: 10 years
• Address and data latches
• Sector erase function: 256 bytes per sector
• Self-timer erase/program
• Byte program time: 35 µs (maximum)
• Write complete detection function: Toggle bit/Data
poling
• Hardware and software data protection functions
• Pin assignment conforms to the JEDEC byte-wide
EEPROM standard.
• Package
SOP 32-pin (525 mil) plastic package: LE28FV4001M
TSOP 42-pin (10 × 14 mm) plastic package:LE28FV4001T
TSOP 40-pin (10×14mm)plastic package: LE28FV4001R
unit: mm
3087A-TSOP40
[LE28FV4001M. T, R]
SANYO: SOP32
SANYO: TSOP40 (TYPE-I)
These FLASH MEMORY products incorporate technology licensed from Silicon Storage Technology, Inc.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
22897HA(OT) No. 5468-1/14
1 page  
LE28FV4001M, T, R-20/25
3. Byte programming operation
The byte programming operation is started by writing a setup command (10H) to the command register.
Once the setup command is executed, the execute command is started by the next WE pulse transition. Figure 7
shows the timing waveforms for this operation. The address and the data are latched internally on the falling edge
and rising edge of the WE pulse, respectively. The WE rising edge also corresponds to the start of the programming
operation. The programming operation is automatically completed under internal timing control. Figures 2 and 7
show the programming characteristics and waveforms.
As mentioned previously, this two-stage sequence in which a setup command and a following execute operation, are
required guarantees that memory cells will not be programmed accidentally.
4. Byte programming flowchart
Data is stored into the device (i.e., the device is programmed) by the byte programming flowchart shown in Figure 2.
The byte programming command sets up the byte for writing. The address is latched on the falling edge of WE or
CE, whichever falls last. The data is latched on the rising edge of WE or CE, whichever rises first, and the
programming operation starts. The application can detect the completion of the write by Data polling or by using the
toggle bit.
5. Reset operation
The reset command is a procedure for safely terminating an erase or programming command sequences. Writing
FFH to the command register after issuing an erase or programming setup command will safely cancel that operation.
The contents of memory will not be changed. The device goes to read mode after executing a reset command. The
reset command cannot activate the software data protect function. Figure 8 shows the timing wavefroms.
6. Read operation
A read operation is performed by setting CE and OE, and then WE to read mode. Figure 3 shows the read mode
timing waveforms, and the read mode conditions are shown as “function logic”. A read cycle from the host searches
for the memory array data. The device remains in the read state until another command is written to the command
register.
As a default, the device will be in read mode in the write protect state from the time power is first applied until a
command is written to the command register. The unprotect sequence must be executed to perform a write operation
(erase or programming).
The read operation is controlled by CE and OE, and both must be set to the logic low level to activate the read
function. When CE is at the logic high level, the chip is in the unselected state and only draws the standby current.
OE controls the output pins. The device output pins will be in the high-impedance state if either CE or OE is at the
logic high level.
7. Read ID operation
The read ID operation consists of a single command, 90H. A read operation from address 0000H will then return the
manufacturer code, BFH and a read operation from address 0001H will return the device code, 04H. This operation
is terminated by writing any other valid command to the command register.
Protecting Data from Unintentional Writes
To protect the accumulated stored data that the user intends to be nonvolatile, the LE28FV4001 Series products provide
both hardware and software functions to prevent unintentional writes when power is applied or cut off.
1. Hardware data protection
The LE28FV4001 Series products incorporate a hardware data function that prevents unintentional writes.
• Write inhibit mode: Write operations are disabled if either OE is at the low logic level, CE is at the high logic level,
or WE is at the high logic level.
• Noise and glitch protection: WE pulses shorter than 15 ns will not execute a write operation.
• The LE28FV4001 Series products were designed to hold unintentional writes to a minimum by setting the device
to read mode as the default when power is first applied.
No. 5468-5/14
5 Page 
LE28FV4001M, T, R-20/25
Figure 3 Read Cycle
Figure 4 WE Control Write Cycle
Figure 5 CE Control Write Cycle
No. 5468-11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LE28FV4001T.PDF ] | |
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