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PDF MAX3634 Data sheet ( Hoja de datos )
| Número de pieza | MAX3634 | |
| Descripción | 622Mbps/1244Mbps Burst-Mode Clock Phase Aligner | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-3818; Rev 0; 9/05
622Mbps/1244Mbps Burst-Mode Clock Phase
Aligner for GPON OLT Applications
www.datasheet4u.com
General Description
The MAX3634 burst-mode clock phase aligner (CPA) is
designed specifically for 622Mbps or 1244Mbps GPON
(ITU G.984) optical line terminal (OLT) receiver applica-
tions. The MAX3634 provides clock and clock-aligned
resynchronized upstream data through differential
LVPECL outputs. Using the OLT system clock as a ref-
erence, the MAX3634 aligns to the input data and
acquires within the first 13 bits of the burst. The CPA
operates with received data that is frequency locked to
the OLT reference. The acquisition time, bit-error ratio,
and jitter tolerance all support GPON PMD specifica-
tions. LVPECL high-speed clock and data outputs pro-
vide compatibility with FPGAs at 622Mbps and with the
MAX3885 deserializer at 1244Mbps.
The MAX3634 is available in a low-profile, 7mm x 7mm,
48-lead TQFN package. The MAX3634 operates from a
single +3.3V supply, over the -40°C to +85°C tempera-
ture range.
Applications
622Mbps GPON OLT Receivers
1244Mbps GPON OLT Receivers
Features
♦ DC-Coupled Clock Phase Aligner for Burst-Mode
GPON Applications
♦ 13-Bit Burst Acquisition Time
♦ 0.85UI High-Frequency Jitter Tolerance
♦ Continuous Clock Output
♦ Byte Rate (1/8th Data Rate) Reference Clock Input
♦ Lock Detect Output
♦ LVPECL Serial Data Input and Output
♦ LVPECL Reset Input
Ordering Information
PART
MAX3634ETM
TEMP RANGE
-40°C to +85°C
PIN-
PACKAGE
48 TQFN
(7mm x 7mm)
PKG
CODE
T4877-6
Pin Configuration appears at end of data sheet.
Typical Application Circuit
BURST RESET
DATA
CLOCK
MAX3634
BURST-MODE
CLOCK PHASE
ALIGNER
BURST-MODE
TIA/LA
UPSTREAM
1244Mbps
DIVIDE BY 8 RATESEL
OLT CLOCK
DATA
MAX3738
CONTINUOUS
LASER DRIVER
GPON OPTICAL LINE TERMINATION
DOWNSTREAM
2488Mbps
BURST ENABLE
MAX3656
BURST-MODE
LASER DRIVER
MAX3892
DATA
SERIALIZER
4 DATA
CLOCK
DIVIDE BY 16
MAX3864
MAX3748A
TIA/LA
MAX3872
SONET
CDR
CLOCK
DATA
GPON OPTICAL NETWORK TERMINATION
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
622Mbps/1244Mbps Burst-Mode Clock Phase
Aligner for GPON OLT Applications
www.datasheet4u.com
General Description
Theory of Operation
The MAX3634 CPA provides serial clock and data out-
puts for GPON upstream bursts.
The burst-mode CPA operates on the principle that the
recovered clock from the ONT CDR is used at each
ONT to clock upstream data bursts out of the ONT con-
troller. The burst-mode CPA has logic that determines
the correct phase relationship between the upstream
data and the OLT reference clock at the beginning of
each ONT’s burst, and resamples the upstream data at
each bit using that clock.
The burst-mode CPA contains a phase-locked loop
(PLL) that synchronizes its oscillator to the reference
clock input. This oscillator drives a phase splitter, which
generates eight evenly spaced phases of the serial
clock, which are used to sample the input data at 1/8th
bit intervals in eight flip-flops. Combinatorial and
sequential logic measures the preamble, and based on
the phase of the preamble, determines which one of
the eight clock phases is at the center of the input data
bits. The data from the flip-flop associated with this
phase is then steered through a multiplexer to the CPA
output, which requires four or five additional clock peri-
ods until valid data is output. The CPA serial output
clock is continuous, without any phase jumps or dis-
continuities from burst to burst.
The burst-mode CPA requires a preamble sequence of
1010101010101 (13 bits) for correct phase alignment.
Typically, output begins after the 12th bit, although for
certain data/phase relationships, 13 bits are required.
An LVPECL-compatible lock status output is provided,
which indicates when the correct phase has been
acquired and valid serial output data is available. This
output remains low until reset by the burst reset input
(RST). The output data is disabled (held low) during the
period between reset and lock.
Reference Clock Input
The MAX3634 includes a PLL, which multiplies the ref-
erence clock by eight for use in the retiming circuitry.
For correct operation, the REFCLK input must be con-
nected to the OLT byte-rate reference clock, which
must be equal to 1/8th the serial data rate, and must
have a 40% to 60% duty cycle. This must be the same
clock source used to time the downstream data, and
the upstream data must be frequency locked to this
source.
The RATESEL input is used to configure 622Mbps or
1244Mbps operation; when RATESEL is high, the
MAX3634 operates at 622Mbps.
REFCLK+
REFCLK-
LVPECL
RATESEL
TTL
SDI+
SDI- LVPECL
RST+
RST- LVPECL
622Mbps/1244Mbps
PLL/PHASE SPLITTER
φ0 φ7
DQ
DQ
DQ
PHASE-ACQUISITION LOGIC
MAX3634
BURST-MODE CPA
SDO+
MUX LVPECL SDO-
SCLK+
LVPECL SCLK-
LOCK+
LVPECL LOCK-
Figure 2. Functional Block Diagram
_______________________________________________________________________________________ 5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MAX3634.PDF ] | |
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