PDF MAX3620 Data sheet ( Hoja de datos )

Número de pieza	MAX3620
Descripción	Delay Lines
Fabricantes	Maxim Integrated Products
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Hay una vista previa y un enlace de descarga de MAX3620 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas
No Preview Available ! 19-3550; Rev 0; 1/05 Delay Lines for High-Speed Clock Distribution Systems General Description www.dTathaeshMeeAt4Xu.3c6om20 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate delays of 0.75ns, 1.00ns, 1.25ns, and 1.50ns for the generation of the quarter clock phase. The MAX3620 is offered in a small 3mm x 3mm package which contains two delay lines of equal length that can be driven either differentially or single-endedly. Applications QDR/QDRII Memory Systems Multiphase Clock Generation TOP VIEW Pin Configuration Features ♦ Supports HSTL Source Terminated Lines ♦ All-Passive Design ♦ Compatible with 100Ω Differential and 50Ω Single- Ended Transmission Lines ♦ Small 3mm x 3mm Package PART MAX3620AETT MAX3620BETT MAX3620CETT MAX3620DETT Ordering Information TEMP RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C PIN-PACKAGE 6 TDFN 6 TDFN 6 TDFN 6 TDFN IN1 1 COMMON 2 IN2 3 MAX3620 EP TDFN EP—EXPOSED PAD. MUST BE CONNECTED TO THE SAME POTENTIAL AS COMMON. 6 OUT1 5 COMMON 4 OUT2 PART MAX3620AETT MAX3620BETT MAX3620CETT MAX3620DETT Selector Guide PKG CODE T633-2 T633-2 T633-2 T633-2 TOP MARK AJX AIY AIZ AJA Typical Application Circuit QDR II SRAM CLOCK OUTPUT HSTL SOURCE TERMINATED 50Ω 50Ω DELAY LINE 1/4 CLOCK PERIOD IN1 OUT1 50Ω COMMON MAX3620 COMMON 50Ω IN2 OUT2 QDR II SRAM CLOCK INPUT HSTL HIGH-Z CMOS 90° PHASE 270° PHASE 50Ω 180° PHASE 50Ω 50Ω 0° PHASE 50Ω ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 page Delay Lines for High-Speed Clock Distribution Systems www.da(TtaAsh=e+et245u°.Cco, munless otherwise noted.) Typical Operating Characteristics (continued) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 10 MAX3620B S22 50MHz 100 FREQUENCY (MHz) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 1000 10 MAX3620C S22 50MHz 100 FREQUENCY (MHz) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 1000 10 MAX3620D S22 50MHz 100 FREQUENCY (MHz) 1000 Pin Description PIN NAME FUNCTION 1 IN1 Single-Ended Input 1 2 COMMON Common 3 IN2 Single-Ended Input 2 4 OUT2 Single-Ended Output 2 5 COMMON Common 6 OUT1 Single-Ended Output 1 — Exposed Connect to same potential as COMMON Pad IN1 COMMON IN2 Figure 1. Functional Diagram Detailed Description The MAX3620 delay lines are transmission lines con- structed with a series of L-C sections. Figure 1 is a functional diagram of the MAX3620. The distributed architecture of the MAX3620 allows for symmetrical impedance looking into each terminal. When the MAX3620 is used in single-ended operation, leave unused input/output open. OUT1 COMMON OUT2 _______________________________________________________________________________________ 5 5 Page

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PDF Descargar	[ Datasheet MAX3620.PDF ]

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