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PDF MAX3540 Data sheet ( Hoja de datos )
| Número de pieza | MAX3540 | |
| Descripción | Complete Single-Conversion Television Tuner | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-0848; Rev 0; 10/07
EVAALVUAAILTAIOBNLEKIT
Complete Single-Conversion Television Tuner
www.datasheet4u.com
General Description
The MAX3540 complete single-conversion television
tuner is designed for use in analog/digital terrestrial appli-
cations and digital set-top boxes. This television tuner
draws only 760mW of power from a +3.3V supply voltage.
The MAX3540 is designed to convert NTSC or ATSC sig-
nals in the 54MHz to 860MHz band to a 44MHz interme-
diate frequency (IF).
The MAX3540 includes a variable-gain low-noise ampli-
fier (LNA), multiband tracking filters, a harmonic-rejec-
tion mixer, a low-noise IF amplifier, an IF power detector,
and a variable-gain IF amplifier. The MAX3540 also
includes fully monolithic VCOs and tank circuits as well
as a complete frequency synthesizer. This highly inte-
grated design allows for low-power tuner-on-board
applications without the cost and power-dissipation
issues of dual-conversion tuner solutions.
The MAX3540 is specified for operation in the 0°C to
+85°C temperature range and is available in a leadless
48-pin flip-chip (fcLGA) package.
Televisions
Applications
Analog/Digital Terrestrial Receivers
Digital Set-Top Boxes
Cable Modems
VOIP Gateways
Features
♦ Low Power Consumption: 760mW (typ) from a
+3.3V Supply Voltage
♦ Integrated Tracking Filters
♦ ATSC A/74 Compliant
♦ 40dB Adjacent Channel Protection Ratio (ACPR)
♦ 4.4dB (typ) Low Noise Figure
♦ Small, 7mm x 7mm, fcLGA Leadless Package
♦ 256-QAM-Compatible Phase-Noise Performance
♦ IF Overload Detector Controls RF Variable-Gain
Amplifier
♦ 2-Wire I2C-Compatible Serial Control Interface
Ordering Information
PART
TEMP
RANGE
PIN-
PACKAGE
PKG
CODE
MAX3540ULM#G42 0°C to +85°C 48 fcLGA-EP* L4877A-E
*EP = Exposed paddle.
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
+
SCL 1
SDA 2
VCC 3
UHF_IN 4
÷ R PD CP
SERIAL
INTERFACE
÷N
VCO
DIVIDER
VHF_IN 5
RFGND2 6
LEXT 7
RFGND3 8
RFAGC 9
VCC 10
GND 11
MAX3540
EP
VREF
+
-
GND 12
36 IFOUT1-
35 IFOUT1+
34 IFOVLD
33 VCC
32 VCC
31 GND
30 IFIN+
29 IFIN-
28 VCC
27 GND
26 IFAGC
25 IFOUT2+
13 14 15 16 17 18 19 20 21 22 23 24
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
Complete Single-Conversion Television Tuner
www.datasheet4u.com
Pin Description
PIN
1
2
3, 10, 23,
28, 32, 33,
37, 41, 44
4
5
6
7
8
9
11–22,
27, 31
24
25
26
29
30
34
35
36
38
39
40
42
43
45
46
47
NAME
SCL
SDA
FUNCTION
2-Wire Serial-Clock Interface. Requires a pullup resistor to VCC.
2-Wire Serial-Data Interface. Requires a pullup resistor to VCC.
VCC Power-Supply Connections. Bypass each supply pin to ground with a 1000pF capacitor.
UHF_IN
VHF_IN
RFGND2
LEXT
RFGND3
RFAGC
UHF RF Input. Matched to 75Ω over the operating band. Requires a DC-blocking capacitor.
VHF RF Input. Matched to 75Ω over the operating band. Requires a DC-blocking capacitor.
RF Ground. Bypass to the PCB’s ground plane with a 1000pF capacitor. Do not connect RFGND2
and RFGND3 together.
RF VGA Supply Voltage. Connect through a 270nH pullup inductor to VCC.
RF Ground. Bypass to the PCB’s ground plane with a 1000pF capacitor. Do not connect RFGND2
and RFGND3 together.
RF AGC Gain-Control Voltage. Accepts a DC voltage from 0.5V (minimum gain) to 3V (maximum gain).
GND
Ground. Connect to the PCB’s ground plane.
IFOUT2- Inverting IF-VGA Output. Connect to the input of an anti-aliasing filter. Requires a DC-blocking capacitor.
IFOUT2+ Noninverting IF-VGA Output. Connect to the input of an anti-aliasing filter. Requires a DC-blocking
capacitor.
IFAGC IF AGC Gain-Control Voltage. Accepts a DC voltage from 0.5V (minimum gain) to 3V (maximum gain).
IFIN-
IFIN+
IFOVLD
IFOUT1+
Inverting IF-VGA Input. Connect to the output of an IF-SAW filter.
Noninverting IF-VGA Input. Connect to the output of an IF-SAW filter.
IF Power Detector Open-Collector Output. Requires a 10kΩ pullup resistor to VCC.
Noninverting IF-LNA Output. Requires a DC-blocking capacitor.
IFOUT1-
LDO
Inverting IF-LNA Output. Requires a DC-blocking capacitor.
VCO LDO Bypass. Bypass to ground with a 0.47μF capacitor.
GND_TUNE VTUNE Ground Connection. Connect to the PCB ground plane. All loop filter component GND must
be connected to this pin (see the Typical Application Circuit).
VTUNE VCO Tuning Input. Connect to the PLL loop filter output.
MUX
CP
Test Output. Leave this pin unconnected during normal operation.
Charge-Pump Output. Connect to the PLL loop filter input.
XTALN
XTALP
Crystal Oscillator Feedback. See the Typical Application Circuit.
Crystal Input. Requires a DC-blocking capacitor.
ADDR1
2-Wire Serial-Interface Address Line 1. This pin along with ADDR2 sets the device address for the
I2C-compatible serial interface.
48
ADDR2
2-Wire Serial-Interface Address Line 2. This pin along with ADDR1 sets the device address for the
I2C-compatible serial interface.
EP EP Exposed Paddle. Solder evenly to the PCB ground plane for proper operation.
_______________________________________________________________________________________ 5
5 Page 
Complete Single-Conversion Television Tuner
www.daTtahseheMet4AuX.c3o5m40 continuously awaits a START condition
followed by its slave address. When the device recog-
nizes its slave address, it acknowledges by pulling the
SDA line low for one clock period. It is ready to accept
or send data depending on the R/W bit (Figure 1).
Write Cycle
When addressed with a write command, the MAX3540
allows the master to write to a single register or to multi-
ple successive registers.
A write cycle begins with the bus master issuing a
START condition followed by the 7 slave address bits
and a write bit (R/W = 0). The MAX3540 issues an ACK
if the slave address byte is successfully received. The
bus master must then send to the slave the address of
the first register it wishes to write to. If the slave
acknowledges the address, the master can then write
one byte to the register at the specified address. Data
is written beginning with the most significant bit. The
MAX3540 again issues an ACK if the data is success-
fully written to the register. The master can continue to
write data to the successive internal registers with the
MAX3540 acknowledging each successful transfer, or it
can terminate transmission by issuing a STOP condi-
tion. The write cycle does not terminate until the master
issues a STOP condition.
Figure 2 illustrates an example in which registers 0
through 2 are written with 0x0E, 0xD8, and 0xE1,
respectively.
Read Cycle
A read cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX3540 issues an
ACK if the slave address byte is successfully received.
The master then sends the 8-bit address of the first reg-
ister that it wishes to read. The MAX3540 then issues
another ACK. Next, the master must issue a START con-
dition followed by the 7 slave address bits and a read
bit (R/W = 1). The MAX3540 issues an ACK if it success-
fully recognizes its address and begins sending data
from the specified register address starting with the
most significant bit (MSB). Data is clocked out of the
MAX3540 on the rising edge of SCL. On the 9th rising
edge of SCL, the master can issue an ACK and contin-
ue reading successive registers or it can issue a NACK
followed by a STOP condition to terminate transmission.
The read cycle does not terminate until the master
issues a STOP condition. Figure 3 illustrates an example
in which registers 0 and 1 are read back.
SLAVE ADDRESS
S
SDA
1
1
0
0
0
ADDR2
ADDR1
R/W
ACK
P
SCL 1 2 3 4 5 6 7 8 9
NOTE: TIMING PARAMETERS CONFORM WITH I2C BUS SPECIFICATIONS.
Figure 1. MAX3540 Slave Address Byte
START
WRITE DEVICE
ADDRESS
11000[ADDR2][ADDR1]
R/W
0
ACK
—
WRITE REGISTER
ADDRESS
0x00
WRITE DATA TO
WRITE DATA TO
WRITE DATA TO
ACK ACK ACK ACK
REGISTER 0x00
REGISTER 0x01
REGISTER 0x02
STOP
— 0x0E — 0xD8 — 0xE1 —
Figure 2. Example: Write registers 0 through 2 with 0x0E, 0xD8, and 0xE1, respectively.
START
WRITE DEVICE
ADDRESS
R/W ACK WRITE 1st REGISTER ACK
ADDRESS
START
WRITE DEVICE
ADDRESS
R/W
ACK
READ DATA
REG 0
ACK
READ DATA
REG 1
110000[ADDR2][ADDR1] 0 — 0x00 —
110000[ADDR2][ADDR1] 1 — D7–D0 — D7–D0
NACK
—
STOP
Figure 3. Example: Read data from registers 0 through 1.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX3540.PDF ] | |
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