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PDF CDK1302 Data sheet ( Hoja de datos )
| Número de pieza | CDK1302 | |
| Descripción | Flash A/D Converter | |
| Fabricantes | Cadeka | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CDK1302 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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Data Sheet
CDK1302
8-bit, 750 MSPS, Flash A/D Converter
Amplify the Human Experience
www.datasheet4u.com
features
n 1:2 Demuxed ECL compatible outputs
n Wide input bandwidth – 900MHz
n Low input capacitance – 15pF
n Metastable errors reduced to 1 LSB
n Monolithic for low cost
n Gray code output
Applications
n Digital oscilloscopes
n Transient capture
n Radar, EW, ECM
n Direct RF down-conversion
Block Diagram
General Description
The CDK1302 is a full parallel (flash) analog-to-digital converter capable
of digitizing full scale (0 to -2V) inputs into eight-bit digital words at an
update rate of 750 MSPS. The ECL-compatible outputs are demultiplexed
into two separate output banks, each with differential data ready outputs
to ease the task of data capture. The CDK1302’s wide input bandwidth and
low capacitance eliminate the need for external track-and-hold amplifiers
for most applications. A proprietary decoding scheme reduces metastable
errors to the 1 LSB level. The CDK1302 operates from a single – 5.2V supply,
with a nominal power dissipation of 5.5W.
The CDK1302 is available in an 80-lead surface-mount MQuad package over
the industrial temperature range (-25°C to +85°C).
Ordering Information
Part Number
CDK1302AEMQ80
CDK1302AEMQ80_Q
CDK1302BEMQ80
CDK1302BEMQ80_Q
Package
MQUAD-80
MQUAD-80
MQUAD-80
MQUAD-80
Moisture sensitivity level for all parts is MSL-1.
Pb-Free
Yes
No
Yes
No
RoHS Compliant
Yes
No
Yes
No
Operating Temperature Range
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
Packaging Method
Rail
Rail
Rail
Rail
©2008 CADEKA Microcircuits LLC
www.cadeka.com
1 page  
Data Sheet
Electrical Characteristics
(TJ = TC = TA = +25°C , VEE = -5.2V, VRB = -2.0V, VRM = -1.0V, VRT = 0.00V, ƒCLK = 750MHz, Duty Cycle=50%,
unless otherwise specified)
Symbol Parameter
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Input High Voltage(1)
Input Low Voltage(1)
tPWH
Clock Pulse Width High(1)
tPWL Clock Pulse Width Low(1)
Digital Outputs
Logic 1 Voltage(1)
Logic 0 Voltage(1)
Rise Time
Fall Time
Power Supply Requirements
VEE Voltage Range(2)
IEE Current(1)
Power Dissipation(1)
Conditions
CLK, CLK
CLK, CLK
20% to 80%
20% to 80%
VIN = 0V
Notes:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
3. Typical Thermal Impedance: θJC = +4°C/W.
CDK1302A
Min Typ Max
-1.1 -0.7
-1.8 -1.5
0.67 0.5
0.67 0.5
-1.1 -0.9
-1.8 -1.5
450
450
-4.95
-5.2
1.05
5.5
-5.45
1.2
6.25
CDK1302B
Min Typ Max
Units
-1.1 -0.7
-1.8 -1.5
0.67 0.5
0.67 0.5
-1.1 -0.9
-1.8 -1.5
450
450
V
V
ns
ns
V
V
ps
ps
-4.95 -5.2 -5.45
1.05 1.2
5.5 6.25
V
A
W
©2008 CADEKA Microcircuits LLC
www.cadeka.com 5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CDK1302.PDF ] | |
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