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PDF S93VP463 Data sheet ( Hoja de datos )
| Número de pieza | S93VP463 | |
| Descripción | (S93VP462 / S93VP463) Voltage Sense Write Protected Memory | |
| Fabricantes | Summit | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de S93VP463 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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VOLTAGE-SENSE™ Write Protected Memory
S93VP462/S93VP463
www.datasheet4u.com
FEATURES
• Voltage-Sense Write Protection
— Low VCC Write Lockout
— All Writes Inhibited when VCC < VTRIP
— Protects Against Inadvertent Writes During
- Power-up
- Power-down
- Brown-out Conditions
— All Devices ‘Readable’ from 1.8V to 5.5V
- User Selectable VTRIP Levels
• Memory
— 1K-bit Microwire Memory
— S93VP462
– Internally Ties ORG Low
– 100% Compatible with All 8-bit
Implementations
– Sixteen Byte Page Write Capability
— S93VP463
– Internally Ties ORG High
– 100% Compatible With all 16-bit
Implementations
– Eight Word Page Write Capability
APPLICATIONS
New designs for applications where data corruption
cannot be permitted.
Replacement of existing industry standard 1K
memories.
OVERVIEW
The S93VP462 and S93VP463 are voltage monitoring
memory devices that write protect the array from inad-
vertent writes whenever VCC is below VTRIP.
Both devices have 1k-bits of E2PROM memory that is
accessible via the industry standard microwire bus. The
S93VP462 is configured with an internal ORG pin tied
low providing a 8-bit byte organization and the
S93VP463 is configured with an internal ORG pin tied
high providing a 16-bit word organization. Both the
S93VP462 and S93VP463 have page write capability.
The devices are designed for a minimum 1,000,000
program/erase cycles and have data retention in ex-
cess of 100 years.
BLOCK DIAGRAM
VCC 8
I
GND 5
+
VTRIP
-
CS 1
SK 2
DI 3
MODE
DECODE
DO 4
DATA I/O
RESET
PULSE
GENERATOR
WRITE
CONTROL
CIRCUITRY
NONVOLATILE
MEMORY
ARRAY
67
NC NC
2040 ILL2.0
SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 1998
2040-01 10/23/98
Characteristics subject to change without notice
1
1 page  
S93VP462/S93VP463
www.datasheet4u.com
SK
CS
AN AN-1
DI 1 0 1
A0 DN
D0
tCS
STATUS
VERIFY
STANDBY
tSV BUSY
tHZ
HIGH-Z
DO READY
HIGH-Z
tEW
2040 ILL 5.0
Figure 3. Write Instruction Timing
SK
CS
AN AN-1
DI 1 1 1
A0
STATUS VERIFY
tCS
STANDBY
tSV tHZ
HIGH-Z
DO BUSY READY
HIGH-Z
tEW
Figure 4. Erase Instruction Timing
2040 ILL6.0
SK
CS STANDBY
DI
1 00
*
* ENABLE=1
DISABLE=00
1
Figure 5. EWEN/EWDS Instruction Timing
5
2040 ILL 7.0
2040-01 10/23/98
5 Page 
S93VP462/S93VP463
Ready/Busy Status
www.datasheet4u.com
During the internal write operation the S93VP462/VP463 memory array is inaccessible. After starting the write
operation (taking CS low) the host can implement a 10ms timeout routine or alternatively it can employ a polling routine
that tests the state of the DO pin.
After starting the write, testing for the status is easily accomplished by taking CS high and testing the state of DO. If
it is low the device is still busy with the internal write. If it is high the write operation has completed.
For the polling routine the host has the option of toggling CS for each test of DO, or it can place CS high and then
intermittently test DO. SK is not required for any of these operations. Once the device is ready, it will continue to drive
DO high whenever the S93VP462/VP463 is selected. The ready state of DO can be cleared by clocking in a start bit;
this start bit can either be the beginning of a new command sequence or it can be a dummy start bit with CS returning
low before the host issues a new command.
SK
CS
STATUS VERIFY
tCS
DI
tSV tHZ
DO
BUSY READY
HIGH-Z
HIGH-Z
t EW
STATUS CLEARED
2040 ILL13.0
2040-01 10/23/98
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet S93VP463.PDF ] | |
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