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PDF NJW1180 Data sheet ( Hoja de datos )
| Número de pieza | NJW1180 | |
| Descripción | AUDIO PROCESSOR | |
| Fabricantes | New Japan Radio | |
| Logotipo |  |
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NJW1180
www.datasheet4u.com
Audio Processor with SRS WOW
s GENERAL DESCRIPTION
The NJW1180 is an audio processor with SRS WOW. It includes
all of functions processing audio signal for TV, such as volume,
balance, tone control and 4ch input selector. All of internal status
and variables are controlled by I2C BUS.
s FEATURES
q Operating Voltage
8 to 13 V
q SRS WOW (including SRS 3D, FOCUS and TruBass function)
q Simulated Stereo
q 4ch Input Selector
q Volume
0 to -80dB (0.5dB/step), MUTE
q Balance
0 to -30dB (1dB/step), MUTE
q Tone Control
-15dB to +15dB(1dB/step)
q I2C BUS Interface
q Bi-CMOS Technology
q Package Outline
QFP48-P1
s BLOCK DIAGRAM
s PACKAGE OUTLINE
NJW1180FP1
IN1a
IN2a
SEL
VOL1
Tone
IN3a
IN4a
AGC
IN1b
IN2b
IN3b
IN4b
SEL
VOL1
Tone
WOW/Simulated
(FOCUS/TruBass/SRS 3D)
VOL2
VOL2
VOL2
Logic
Bias
CVO
CBA
CTH
CTL
CSR
CTB
CFCS
V+
GND
–1–
1 page  
NJW1180
s I2C BUS CHARACTERISTICS (SDA, SCL)
I2C BUS Load Conditions: Pull up resistance 4k (Connected to +5V), Load capacitance 200pF (Connected to GND)
PARAMETER
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Low Level Input Voltage
SYM
BOL
VIL
STANDARD MODE
MIN. TYP. MAX.
0.0 - 1.5
FAST MODE
UNIT
MIN. TYP. MAX.
0.0 - 1.5 V
High Level Input Voltage
VIH 2.7 - 5.0 2.7 - 5.0 V
Hysteresis of Schmitt trigger inputs
Vhys
-
-
- 0.25 -
-
V
LOW level output voltage (3mA at SDA pin)
VOL 0
- 0.4 0
- 0.4 V
Output fall time from VIHmin to VILmax with
a bus capacitance from 10pF to 400pF
tof
-
- 250 20
- 250 ns
+0.1Cb
Pulse width of spikes which must be suppressed by the input
filter
tSP
-
-
-
0
- 50 ns
Input current each I/O pin with an input voltage between
0.1VDD and 0.9VDDmax
Ii
-10 -
10 -10 -
10 µA
Capacitance for each I/O pin
Ci - - 10 - - 10 pF
SCL clock frequency
fSCL
-
- 100 -
- 400 kHz
Hold time (repeated) START condition.
tHD:STA 4.0
-
- 0.6 -
- µs
LOW period of the SCL clock
tLOW 4.7
-
- 1.3 -
- µs
HIGH period of the SCL clock
tHIGH 4.0
-
- 0.6 -
- µs
Set-up time for a repeated START condition
tSU:STA 4.7
-
- 0.6 -
- µs
Data hold time
tHD:DAT
0
- 3.45 0
- 0.9 µs
Data set-up time
tSU:DAT 250
-
- 100 -
- ns
Rise time of both SDA and SCL signals
tr - - 1000 - - 300 ns
Fall time of both SDA and SCL signals
tf - - 300 - - 300 ns
Set-up time for STOP condition
tSU:STO
Bus free time between a STOP and START
condition
tBUF
4.0
4.7
-
-
- 0.6 -
- 1.3 -
- µs
- µs
Capacitive load for each bus line
Cb -
- 400 -
- 400 pF
Noise margin at the LOW level
VnL 0.5
-
- 0.5 -
-
V
Noise margin at the HIGH level
VnH 1
- -1- -V
Cb ; total capacitance of one bus line in pF.
SDA
tf tr
SCL
tHD:STA
S
tLOW
tSU:DAT
tf
tHD:STA
tHD:DAT
tHIGH
tSU:STA
Sr
tSP tr
tBUF
tSU:STO
P
S
–5–
5 Page 
NJW1180
s Master Volume (Select Address: 00H)
VOL
Gain(dB)
HEX
D7
D6
D5
D4
D3
D2
D1
D0
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0 FF 1 1 1 1 1 1 1 1
-1 FD
1
1
1
1
1
1
0
1
-2 FB 1 1 1 1 1 0 1 1
-3 F9
1
1
1
1
1
0
0
1
-4 F7
1
1
1
1
0
1
1
1
-5 F5
1
1
1
1
0
1
0
1
-6 F3
1
1
1
1
0
0
1
1
-7 F1
1
1
1
1
0
0
0
1
-8 EF 1 1 1 0 1 1 1 1
-9 ED 1 1 1 0 1 1 0 1
-10 EB
1
1
1
0
1
0
1
1
-11 E9
1
1
1
0
1
0
0
1
-12 E7
1
1
1
0
0
1
1
1
-13 E5
1
1
1
0
0
1
0
1
-14 E3
1
1
1
0
0
0
1
1
-15 E1
1
1
1
0
0
0
0
1
-16 DF
1
1
0
1
1
1
1
1
-17 DD
1
1
0
1
1
1
0
1
-18 DB
1
1
0
1
1
0
1
1
-19 D9
1
1
0
1
1
0
0
1
-20 D7
1
1
0
1
0
1
1
1
-21 D5
1
1
0
1
0
1
0
1
-22 D3
1
1
0
1
0
0
1
1
-23 D1
1
1
0
1
0
0
0
1
-24 CF
1
1
0
0
1
1
1
1
-25 CD
1
1
0
0
1
1
0
1
-26 CB
1
1
0
0
1
0
1
1
-27 C9
1
1
0
0
1
0
0
1
-28 C7
1
1
0
0
0
1
1
1
-29 C5
1
1
0
0
0
1
0
1
-30 C3
1
1
0
0
0
0
1
1
-31 C1
1
1
0
0
0
0
0
1
-32 BF
1
0
1
1
1
1
1
1
-33 BD
1
0
1
1
1
1
0
1
-34 BB
1
0
1
1
1
0
1
1
-35 B9
1
0
1
1
1
0
0
1
-36 B7
1
0
1
1
0
1
1
1
-37 B5
1
0
1
1
0
1
0
1
-38 B3
1
0
1
1
0
0
1
1
-39 B1
1
0
1
1
0
0
0
1
-40 AF
1
0
1
0
1
1
1
1
-41 AD
1
0
1
0
1
1
0
1
-42 AB
1
0
1
0
1
0
1
1
– 11 –
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet NJW1180.PDF ] | |
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