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VS1053B fiches techniques PDF

VLSI - Ogg Vorbis/MP3/AAC/WMA/MIDI AUDIO CODEC

Numéro de référence VS1053B
Description Ogg Vorbis/MP3/AAC/WMA/MIDI AUDIO CODEC
Fabricant VLSI 
Logo VLSI 





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VS1053B fiche technique
VS1053b Datasheet
VS1053b -
Ogg Vorbis/MP3/AAC/WMA/FLAC/
MIDI AUDIO CODEC CIRCUIT
Features
Description
Decodes
VS1053b is an Ogg Vorbis/MP3/AAC/WMA/
Ogg Vorbis;
FLAC/WAVMIDI audio decoder as well as an
MP3 = MPEG 1 & 2 audio layer III (CBR PCM/IMA ADPCM/Ogg Vorbis encoder on a
+VBR +ABR);
single chip. It contains a high-performance,
MP1/MP2 = layers I & II optional;
proprietary low-power DSP processor core
MPEG4 / 2 AAC-LC(+PNS),
VS_DSP4, data memory, 16 KiB instruction
HE-AAC v2 (Level 3) (SBR + PS);
RAM and 0.5+ KiB data RAM for user appli-
WMA 4.0/4.1/7/8/9 all profiles (5-384 kbps); cations running simultaneously with any built-
General MIDI 1 / SP-MIDI format 0 files; in decoder, serial control and input data in-
FLAC with software plugin;
terfaces, upto 8 general purpose I/O pins, an
WAV (PCM + IMA ADPCM)
UART, as well as a high-quality variable-sample-
Encodes Ogg Vorbis w/ software plugin rate stereo ADC (mic, line, line + mic or 2×line)
Encodes stereo IMA ADPCM / PCM
and stereo DAC, followed by an earphone am-
Streaming support for MP3 and WAV
plifier and a common voltage buffer.
EarSpeaker Spatial Processing
Bass and treble controls
VS1053b receives its input bitstream through
a serial input bus, which it listens to as a
Operates with a single 12..13 MHz clock system slave. The input stream is decoded
Can also be used with a 24..26 MHz clock and passed through a digital volume control
Internal PLL clock multiplier
to an 18-bit oversampling, multi-bit, sigma-
Low-power operation
High-quality on-chip stereo DAC with no
phase error between channels
Zero-cross detection for smooth volume
change
delta DAC. The decoding is controlled via a
serial control bus. In addition to the basic de-
coding, it is possible to add application spe-
cific features, like DSP effects, to the user
RAM memory.
Stereo earphone driver capable of driv-
ing a 30 load
Quiet power-on and power-off
I2S output interface for external DAC
Optional factory-programmable unique chip
ID provides basis for digital rights manage-
ment or unit identification features.
Separate voltages for analog, digital, I/O
On-chip RAM for user code and data
Serial control and data interfaces
Can be used as a slave co-processor
SPI flash boot for special applications
UART for debugging purposes
New functions may be added with soft-
ware and upto 8 GPIO pins
Lead-free RoHS-compliant package
Version: 1.22, 2014-12-19
1

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