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PDF HD64F7051 Data sheet ( Hoja de datos )
| Número de pieza | HD64F7051 | |
| Descripción | 32-Bit RISC Microcomputer | |
| Fabricantes | Renesas Technology | |
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REJ09B0273-0500
www.datasheet4u.com
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
SH7050 Group, SH7050F-ZTAT™,
SH7051F-ZTAT™
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH RISC engine Family/SH7050 Series
HD6437050
HD64F7050
HD64F7051
Rev. 5.00
Revision Date: Jan 06, 2006
1 page  
Main Revisions for This Edition
www.datasheet4u.com
Item
Page
All
2.3.3 Instruction 35
Format
Table 2.9
Instruction Formats
Revision (See Manual for Details)
All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and
other Hitachi brand names changed to Renesas Technology Corp.
Changes due to change in package codes.
FP-168B → PRQP0168JA-A
Table amended
Instruction Formats
d format
15
xxxx xxxx dddd
0
dddd
Source
Operand
—
Destination
Operand
dddddddd: PC
relative
13.2.8 Bit Rate
Register (BRR)
385
22.2 DC
Characteristics
Table 22.2 DC
Characteristics
655
Table 22.3
Permitted Output
Current Values
656
d12 format
15
xxxx dddd
dddd
0
dddd
—
dddddddddddd:
PC relative
Description amended
Synchronous mode:
φ
N = 8 × 22n−1 × B
× 106 − 1
Table amended
Item
Reference
power
supply
current
Pin
During A/D
conversion
Symbol Min
AIref
—
Typ Max
1.0 5
Unit
mA
Table amended
Item
Symbol Min Typ Max
Output low-level permissible current (per pin) IOL
— — 8.0
Note: To assure LSI reliability, do not exceed the output values listed in this table.
Unit
mA
Rev. 5.00 Jan 06, 2006 page v of xx
5 Page 
9.3.10 Number of Bus Cycle States and DREQ Pin Sample Timing.............................. 169
9.3.11 Source Address Reload Function ......................................................................... 186
www.dat9a.s3h.e1e2t4uD.cMomA Transfer Ending Conditions....................................................................... 188
9.3.13 DMAC Access from CPU.................................................................................... 189
9.4 Examples of Use ............................................................................................................... 189
9.4.1 Example of DMA Transfer between On-Chip SCI and External Memory .......... 189
9.4.2 Example of DMA Transfer between External RAM and External Device
with DACK .......................................................................................................... 190
9.4.3 Example of DMA Transfer between A/D Converter and Internal Memory
(Address Reload On)............................................................................................ 190
9.4.4 Example of DMA Transfer between External Memory and SCI1 Send Side
(Indirect Address On) .......................................................................................... 192
9.5 Cautions on Use ................................................................................................................ 194
Section 10 Advanced Timer Unit (ATU) ..................................................................... 195
10.1 Overview........................................................................................................................... 195
10.1.1 Features................................................................................................................ 195
10.1.2 Block Diagrams ................................................................................................... 200
10.1.3 Inter-Channel and Inter-Module Signal Connection Diagram ............................. 208
10.1.4 Prescaler Diagram................................................................................................ 209
10.1.5 Pin Configuration................................................................................................. 210
10.1.6 Register and Counter Configuration .................................................................... 212
10.2 Register Descriptions ........................................................................................................ 216
10.2.1 Timer Start Register (TSTR)................................................................................ 216
10.2.2 Timer Mode Register (TMDR) ............................................................................ 218
10.2.3 Prescaler Register 1 (PSCR1) .............................................................................. 220
10.2.4 Timer Control Registers (TCR) ........................................................................... 221
10.2.5 Timer I/O Control Registers (TIOR).................................................................... 225
10.2.6 Trigger Selection Register (TGSR)...................................................................... 233
10.2.7 Timer Status Registers (TSR) .............................................................................. 235
10.2.8 Timer Interrupt Enable Registers (TIER) ............................................................ 252
10.2.9 Interval Interrupt Request Register (ITVRR)....................................................... 264
10.2.10 Down-Count Start Register (DSTR) .................................................................... 267
10.2.11 Timer Connection Register (TCNR).................................................................... 271
10.2.12 Free-Running Counters (TCNT) .......................................................................... 274
10.2.13 Input Capture Registers (ICR) ............................................................................. 276
10.2.14 General Registers (GR)........................................................................................ 277
10.2.15 Down-Counters (DCNT) ..................................................................................... 278
10.2.16 Offset Base Register (OSBR) .............................................................................. 279
10.2.17 Cycle Registers (CYLR) ...................................................................................... 280
10.2.18 Buffer Registers (BFR) ........................................................................................ 281
Rev. 5.00 Jan 06, 2006 page xi of xx
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