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Número de pieza | WED3EG7218S-JD3 | |
Descripción | 128MB - 16Mx72 DDR SDRAM UNBUFFERED | |
Fabricantes | White Electronic Designs | |
Logotipo | ||
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WED3EG7218S-JD3
PRELIMINARY*
128MB – 16Mx72 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
DDR200, DDR266, DDR333 and DDR400
• JEDEC design specified
BI-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply:
• VCC = VCCQ = 2.5V±0.2V
(100, 133 and 166MHz)
• VCC = VCCQ = 2.6V±0.1V
(200MHz)
JEDEC 184 pin DIMM package
• JD3 PCB height: 30.48 (1.20") Max
NOTE: Consult factory for availability of:
• RoHS Products
• Vendor source control options
• Industrial temperature option
DESCRIPTION
The WED3EG7218S is a 16Mx72 Double Data Rate
SDRAM memory module based on 128Mb DDR SDRAM
component. The module consists of nine 16Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Clock Speed
CL-tRCD-tRP
DDR400 @CL=3
200MHz
3-3-3
OPERATING FREQUENCIES
DDR333 @CL=2.5
DDR266 @CL=2
166MHz
2.5-3-3
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
June 2006
Rev. 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page Whitewww.datasheet4u.com Electronic Designs
WED3EG7218S-JD3
PRELIMINARY
ICC SPECIFICATIONS AND TEST CONDITIONS
DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V includes DDR SDRAM component only
Parameter
Operating
Current
Operating
Current
Symbol Conditions
One device bank; Active =
Precharge; TRC=TRC(MIN);
ICC0
TCK=TCK(MIN); DQ,DM and DQS
inputs changing once per clock cycle;
Address and control inputs changing
once every two cycles
One device bank; Active-read-
Precharge; Burst = 2; TRC=TRC(MIN);
ICC1 TCK=TCK(MIN); lout=0mA; Address
and control inputs changing once per
clock cycle
DDR400@
CL=3
Max
DDR333@
CL=2.5
Max
DDR266@
CL=2
Max
990
1260
DDR266@
CL=2.5
Max
990
1260
DDR200@
CL=2
Max
810
1035
Precharge
Power-Down
Standby
Current
Idle Standby
Current
ICC2P
All device banks idle; Power-down
mode; TCK=TCK(MIN); CKE=(low)
CS# = High; All device banks idle;
TCK=TCK(MIN); CKE=high; Address
ICC2F and other control inputs changing
once per clock cycle. VIN = VREF for
DQ, DQS and DM.
270 270 255
495 495 405
Active Power-
Down Standby
Current
Active Standby
Current
Operating
Current
Operating
Current
ICC3P
One device bank active; Power-down
mode; TCK(MIN); CKE=(low)
CS# = High; CKE = High; One
device bank; Active-Precharge; TRC
= TRAS(MAX); TCK = TCK(MIN); DQ,
ICC3N DM and DQS inputs changing twice
per clock cycle; Address and other
control inputs changing once per
clock cycle.
Burst = 2; Reads; Continous burst;
One device bank active; Address
ICC4R and control inputs changing once per
clock cycle;
TCK = TCK(MIN); lout = 0mA
Burst = 2; Writes; Continous burst;
One device bank active; Address
ICC4W
and control inputs changing once per
clock cycle; TCK = TCK(MIN); DQ, DM
and DQS inputs changing twice per
clock cycle.
315 315 270
540 540 450
1800 1800 1485
1935 1935 1530
Auto Refresh
Current
Self Refresh
Current
ICC5 TRC = TRC(MIN)
ICC6 CKE ≤ 0.2V
Standard
Low Power
1935 1935 1530
18 18 18
999
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
June 2006
Rev. 2
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page Whitewww.datasheet4u.com Electronic Designs
WED3EG7218S-JD3
PRELIMINARY
PART NUMBERING GUIDE
WEDC
MEMORY (SDRAM)
DDR
GOLD
DEPTH
BUS WIDTH
2.5V
SPEED (Mb/s)
PACKAGE 184 PIN
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
WED 3 E G 72M 18 S xxx JD3 x x G
June 2006
Rev. 2
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page |
Páginas | Total 12 Páginas | |
PDF Descargar | [ Datasheet WED3EG7218S-JD3.PDF ] |
Número de pieza | Descripción | Fabricantes |
WED3EG7218S-JD3 | 128MB - 16Mx72 DDR SDRAM UNBUFFERED | White Electronic Designs |
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