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PDF MAX1144 Data sheet ( Hoja de datos )

Número de pieza MAX1144
Descripción (MAX1144 / MAX1145) 14-Bit ADCs
Fabricantes Maxim Integrated Products 
Logotipo Maxim Integrated Products Logotipo



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No Preview Available ! MAX1144 Hoja de datos, Descripción, Manual

19-2465; Rev 0; 4/02
14-Bitwww.DataSheet4U.com ADCs, 150ksps, 3.3V Single Supply
General Description
The MAX1144/MAX1145 are 150ksps, 14-bit ADCs.
These serially interfaced ADCs connect directly to
SPI™, QSPI™, and MICROWIRE™ devices without
external logic. They combine an input scaling network,
internal track/hold, clock, and three general-purpose
digital output pins (for external multiplexer or PGA con-
trol) in a 20-pin SSOP package. The excellent dynamic
performance (THD 90dB), high speed (150ksps in
bipolar mode), and low power (8.0mA) of these ADCs
make them ideal for applications such as industrial
process control, instrumentation, and medical applica-
tions.
The MAX1144 accepts input signals of 0 to +6V (unipo-
lar) or ±6V (bipolar), while the MAX1145 accepts input
signals of 0 to +2.048V (unipolar) or ±2.048V (bipolar).
Operating from a single 3.135V to 3.465V analog digital
supply, powerdown modes reduce current consump-
tion to 0.15mA at 10ksps and further reduce supply
current to less than 20µA slower data rates.
A serial strobe output (SSTRB) allows direct connection
to the TMS320 family digital-signal processors. The
MAX1144/MAX1145 user can select either the internal
clock or an external serial-interface clock for the ADC to
perform analog-to-digital conversions.
The MAX1144/MAX1145 feature internal calibration cir-
cuitry to correct linearity and offset errors. On-demand
calibration allows the user to optimize performance.
Three user-programmable logic outputs are provided
for the control of an 8-channel mux or PGA.
The MAX1144/MAX1145 are available in a 20-pin SSOP
package and are fully specified over the -40°C to
+85°C temperature range.
Applications
Industrial Process Control
Industrial I/O Modules
Data-Acquisition Systems
Medical Instruments
Portable and Battery-Powered Equipment
Functional Diagram and Typical Application Circuit appear
at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor, Corp.
Features
o 150ksps (Bipolar) and 125ksps (Unipolar)
Sampling ADC
o 14 Bits, No Missing Codes
o 1LSB INL Guaranteed
o -100dB THD
o 3.3V Single-Supply Operation
o Low-Power Operation
5mA typ (Unipolar Mode)
o 1.2µA Shutdown Mode
o Software-Configurable Unipolar and Bipolar Input
Ranges
0 to +6V and ±6V (MAX1144)
0 to +2.048V and ±2.048V (MAX1145)
o Internal or External Clock
o SPI/QSPI/MICROWIRE TMS320-Compatible Serial
Interface
o Three User-Programmable Logic Outputs
o Small 20-Pin SSOP Package
Ordering Information
PART
MAX1144ACAP
MAX1144BCAP
MAX1144AEAP
MAX1144BEAP
TEMP
RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
20 SSOP
20 SSOP
20 SSOP
20 SSOP
INL
(LSB)
±1
±2
±1
±2
Ordering Information continued at end of data sheet.
Pin Configuration
TOP VIEW
REF 1
AVDD 2
AGND 3
AVDD 4
DGND 5
SHDN 6
P2 7
P1 8
PO 9
SSTRB 10
MAX1144
MAX1145
SSOP
20 AIN
19 AGND
18 CREF
17 CS
16 DIN
15 DVDD
14 DGND
13 SCLK
12 RST
11 DOUT
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX1144 pdf
14-Bitwww.DataSheet4U.com ADCs, 150ksps, 3.3V Single Supply
TIMING CHARACTERISTICS (Figures 5 and 6) (continued)
(AVDD = DVDD = 3.3V ±5%, TA = TMIN to TMAX, unless otherwise noted.)
Note 1: Tested at AVDD = DVDD = 3.3V, bipolar input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset
error have been nullified.
Note 3: Offset nullified.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Includes
the acquisition time.
Note 5: Acquisition time is 5 clock cycles in short acquisition mode and 13 clock cycles in long acquisition mode.
Note 6: Performance is limited by the converters noise floor, typically 300µVP-P.
Note 7: When an external reference has a different voltage than the specified typical value, the full scale of the ADC scales propor-
tionally.
Note 8: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.
Typical Operating Characteristics
(MAX1144/MAX1145, AVDD = DVDD = 3.3V, fSCLK = 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps),
bipolar input, REF = 2.048V, 4.7µF on REF, 1µF on CREF, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
1
3413 6825 10237 13649
1707 5119 8531 11943 15355
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
1
3413 6825 10237 13649
1707 5119 8531 11943 15355
DIGITAL OUTPUT CODE
TOTAL SUPPLY CURRENT
vs. TEMPERATURE
9.0
A: AVDD, DVDD = 3.135V
8.9 B: AVDD, DVDD = 3.3V
8.8 C: AVDD, DVDD = 3.465V
8.7
C
8.6
8.5 B
8.4
8.3 A
8.2
8.1
8.0
-40
-20 0 20 40 60
TEMPERATURE (°C)
80
_______________________________________________________________________________________ 5

5 Page





MAX1144 arduino
14-Bitwww.DataSheet4U.com ADCs, 150ksps, 3.3V Single Supply
CS
SCLK
DIN
SSTRB
DOUT
tACQ
14
8
START
UNI/
BIP
INT/
EXT
M1
M0
P2
P1
P0
tCONV
9 21 24
B13
MSB
B12
B2
B1
B0
LSB
X
X
FILLED WITH
ZEROS
Figure 5. Internal Clock Mode Timing, Short Acquisition, Bipolar Mode
CS
SSTRB
tCONV
tCSH
tCSS
tSCK
SCLK
tSSTRB
P0 CLOCKED IN
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 6. Internal Clock Mode SSTRB Detailed Timing
In long acquisition mode, SSTRB pulses high for one
clock period after the 15th falling edge of SCLK follow-
ing the start bit. The MSB of the conversion is available
at DOUT on the 16th falling edge of SCLK (Figure 3).
In external clock mode, SSTRB is high impedance
when CS is high (Figure 4). In external clock mode, CS
is normally held low during the entire conversion. If CS
goes high during the conversion SCLK is ignored until
CS goes low. This allows external clock mode to be
used with 8-bit bytes.
Internal Clock
In internal clock mode, the MAX1144/MAX1145 generate
their own conversion clock. This frees the microprocessor
from the burden of running the SAR conversion clock,
and allows the conversion results to be read back at the
processors convenience, at any clock rate up to 4MHz.
SSTRB goes low at the start of the conversion and goes
high when the conversion is complete. SSTRB will be
low for a maximum of 7µs, during which time SCLK
should remain low for best noise performance. An inter-
nal register stores data when the conversion is in
progress. SCLK clocks the data out of the internal stor-
age register at any time after the conversion is complete.
The MSB of the conversion is available at DOUT when
SSTRB goes high. The subsequent 13 falling edges on
SCLK shift the remaining bits out of the internal storage
register (Figure 5). CS does not need to be held low
once a conversion is started.
______________________________________________________________________________________ 11

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