|
|
PDF H83935 Data sheet ( Hoja de datos )
| Número de pieza | H83935 | |
| Descripción | (H83935 - H83937) Hardware Manual | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de H83935 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
1 page  
Contents
Section 1 Overview............................................................................................................
1.1 Overview ............................................................................................................................
1.2 wInwtwer.DnaltaBSlhoecekt4DU.icaogmram ......................................................................................................
1.3 Pin Arrangement and Functions.........................................................................................
1.3.1 Pin Arrangement ...................................................................................................
1.3.2 Pin Functions.........................................................................................................
1
1
5
6
6
7
Section 2 CPU ..................................................................................................................... 13
2.1 Overview ............................................................................................................................ 13
2.1.1 Features ................................................................................................................. 13
2.1.2 Address Space....................................................................................................... 14
2.1.3 Register Configuration .......................................................................................... 14
2.2 Register Descriptions ......................................................................................................... 15
2.2.1 General Registers .................................................................................................. 15
2.2.2 Control Registers................................................................................................... 15
2.2.3 Initial Register Values........................................................................................... 16
2.3 Data Formats ...................................................................................................................... 17
2.3.1 Data Formats in General Registers ....................................................................... 18
2.3.2 Memory Data Formats .......................................................................................... 19
2.4 Addressing Modes.............................................................................................................. 20
2.4.1 Addressing Modes................................................................................................. 20
2.4.2 Effective Address Calculation............................................................................... 22
2.5 Instruction Set .................................................................................................................... 26
2.5.1 Data Transfer Instructions..................................................................................... 28
2.5.2 Arithmetic Operations........................................................................................... 30
2.5.3 Logic Operations................................................................................................... 31
2.5.4 Shift Operations .................................................................................................... 31
2.5.5 Bit Manipulations.................................................................................................. 33
2.5.6 Branching Instructions .......................................................................................... 37
2.5.7 System Control Instructions.................................................................................. 39
2.5.8 Block Data Transfer Instruction............................................................................ 40
2.6 Basic Operational Timing .................................................................................................. 42
2.6.1 Access to On-Chip Memory (RAM, ROM) ......................................................... 42
2.6.2 Access to On-Chip Peripheral Modules................................................................ 43
2.7 CPU States ......................................................................................................................... 45
2.7.1 Overview............................................................................................................... 45
2.7.2 Program Execution State....................................................................................... 46
2.7.3 Program Halt State ................................................................................................ 46
2.7.4 Exception-Handling State ..................................................................................... 46
i
5 Page 
11.4 Interrupts ............................................................................................................................ 323
11.5 Typical Use ........................................................................................................................ 323
11.6 Application Notes............................................................................................................... 327
Section 12 FLEX™ Roaming Decoder II ..................................................................... 329
12.1 Overview ............................................................................................................................ 329
w1w2.w1..D1ataFSehaeteutr4eUs..c..o.m............................................................................................................. 329
12.1.2 System Block Diagram ......................................................................................... 330
12.1.3 Functional Block Diagram .................................................................................... 332
12.2 SPI Packets............................................................................................................................ 333
12.2.1 Packet Communication Initiated by the Host ....................................................... 333
12.2.2 Packet Communication Initiated by the FLEX decoder ....................................... 334
12.2.3 Host-to-Decoder Packet Map................................................................................ 336
12.2.4 Decoder-to-Host Packet Map................................................................................ 338
12.3 Host-to-Decoder Packet Descriptions ................................................................................ 338
12.3.1 Checksum Packet .................................................................................................. 338
12.3.2 Configuration Packet............................................................................................. 341
12.3.3 Control Packet....................................................................................................... 344
12.3.4 All Frame Mode Packet ........................................................................................ 345
12.3.5 Operator Messaging Address Enable Packet ........................................................ 347
12.3.6 Roaming Control Packet ....................................................................................... 347
12.3.7 Timing Control Packet .......................................................................................... 350
12.3.8 Receiver Line Control Packet ............................................................................... 351
12.3.9 Receiver Control Configuration Packets............................................................... 351
12.3.10 Frame Assignment Packets ................................................................................... 355
12.3.11 User Address Enable Packet ................................................................................. 356
12.3.12 User Address Assignment Packets........................................................................ 357
12.4 Decoder-to-Host Packet Descriptions ................................................................................ 358
12.4.1 Block Information Word Packet ........................................................................... 359
12.4.2 Address Packet ...................................................................................................... 360
12.4.3 Vector Packet ........................................................................................................ 361
12.4.4 Message Packet..................................................................................................... 366
12.4.5 Roaming Status Packet ......................................................................................... 366
12.4.6 Receiver Shutdown Packet ................................................................................... 369
12.4.7 Status Packet ......................................................................................................... 370
12.4.8 Part ID Packet ....................................................................................................... 372
12.5 Application Notes............................................................................................................... 374
12.5.1 Receiver Control ................................................................................................... 374
12.5.2 Message Building.................................................................................................. 377
12.5.3 Building a Fragmented Message........................................................................... 379
12.5.4 Operation of a Temporary Address....................................................................... 382
12.5.5 Using the Receiver Shutdown Packet ................................................................... 384
12.6 Timing Diagrams (Reference Data) ................................................................................... 387
vii
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet H83935.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| H83935 | (H83935 - H83937) Hardware Manual | Hitachi Semiconductor |
| H83936 | (H83935 - H83937) Hardware Manual | Hitachi Semiconductor |
| H83937 | (H83935 - H83937) Hardware Manual | Hitachi Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |