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PDF HYB39S64800BTL Data sheet ( Hoja de datos )
| Número de pieza | HYB39S64800BTL | |
| Descripción | 64-MBit Synchronous DRAM | |
| Fabricantes | Infineon Technologies | |
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64-MBit Synchronous DRAM
HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
• High Performance:
fCKMAX
tCK3
tAC3
tCK2
tAC2
-7.5 -8 Units
133 125 MHz
7.5 8 ns
5.4 6 ns
10 10 ns
6 6 ns
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C operating temperature
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2, 3
• Programmable Wrap Sequence: Sequential
or Interleave
• Programmable Burst Length: 1, 2, 4, 8
• Full page (optional) for sequential wrap
around
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command
• Data Mask for Read/Write Control (x4, x8)
• Data Mask for Byte Control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 4096 Refresh Cycles / 64 ms
• Random Column Address every CLK
(1-N Rule)
• Single 3.3 V ± 0.3 V Power Supply
• LVTTL Interface
• Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
• -7.5 version for PC133 3-3-3 application
-8 version for PC100 2-2-2 applications
The HYB 39S64400/800/160BT are four bank Synchronous DRAM’s organized as
4 banks × 4MBit ×4, 4 banks × 2 MBit ×8 and 4 banks × 1 Mbit ×16 respectively. These synchron-
ous devices achieve high speed data transfer rates by employing a chip architecture that prefects
multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using
the Infineon advanced 0.2 µm 64 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for Synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rates than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3 V ± 0.3 V power supply and are available in TSOPII packages.
Data Book
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HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Column Address
Counter
Column Addresses
A0 - A8, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column Address
Buffer
Row Address
Buffer
Refresh Counter
Row Decoder
Memory
Array
Bank 0
4096 x 512
x 8 Bit
Row Decoder
Memory
Array
Bank 1
4096 x 512
x 8 Bit
Row Decoder
Memory
Array
Bank 2
4096 x 512
x 8 Bit
Row Decoder
Memory
Array
Bank 3
4096 x 512
x 8 Bit
Input Buffer Output Buffer
DQ0 - DQ7
Block Diagram: 4 Bank × 2M × 8 SDRAM
Control Logic &
Timing Generator
SPB03697
Data Book
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HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The
following power on and initialization sequence guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and
initialized in a predefined manner.During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The
power on voltage must not exceed VDD + 0.3 V on any of the input pins or VDD supplies. The CLK
signal must be started at the same time. After power on, an initial pause of 200 µs is required
followed by a precharge of both banks using the precharge command. To prevent data contention
on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the
initial pause period. Once all banks have been precharged, the Mode Register Set Command must
be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also
required.These may be done before or after programming the Mode Register. Failure to follow these
steps may lead to unpredictable start-up modes.
Programming the Mode Register
The Mode register designates the operation mode at the read or write cycle. This register is divided
into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency
Field to set the access time at clock cycle and a Operation mode field to differentiate between
normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode. The
mode set operation must be done before any activate command after the initial power up. Any
content of the mode register can be altered by re-executing the mode set command. All banks must
be in precharged state and CKE must be high at least one clock before the mode set operation. After
the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and
WE at the positive edge of the clock activate the mode set operation. Address input data at this
timing defines parameters to be set as shown in the previous table.
Read and Write Operation
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS
low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either
a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 133 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page, where full
page is an optional feature in this device. Column addresses are segmented by the burst length and
serial data accesses are done within this boundary. The first column address to be accessed is
supplied at the CAS timing and the subsequent addresses are generated automatically by the
programmed burst length and its sequence. For example, in a burst length of 8 with interleave
sequence, if the first address is ‘2’, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using the sequential burst type and page length is a
function of the I/O organization and column addressing. Full page burst operation do not self
Data Book
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