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PDF LM1291N Data sheet ( Hoja de datos )
| Número de pieza | LM1291N | |
| Descripción | Video PLL System for Continuous-Sync Monitors | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 1995
LM1291
Video PLL System for Continuous-Sync Monitors
General Description
The LM1291 is an integrated horizontal time base solution
specifically designed to operate in continuous-sync video
monitors It automatically synchronizes to any H frequency
from 22 kHz to 125 kHz and provides the drive pulse to the
high power deflection circuit
Available sync processing includes a vertical sync separator
and a composite video sync stripper An internal sync selec-
tion scheme gives highest priority to separate H and V sync
then composite sync and finally sync on video no external
switching between sync sources is necessary The LM1291
provides polarity-normalized H HV and V sync outputs
along with logic flags which show the respective input polar-
ities
The design uses an on-chip FVC (Frequency-to-Voltage
Converter) to set the center frequency of the VCO (Voltage-
Controlled Oscillator) This technique allows autosync oper-
ation over the entire frequency range using just one opti-
mized set of external components
The system includes a second phase detector which com-
pensates for storage time variation in the horizontal output
transistor the picture’s horizontal position is thus indepen-
dent of temperature and component variance
The LM1291 provides DC control pins for H Drive duty cycle
and flyback phase
Features
Y Wide continuous autosync range 22 kHz to 125 kHz
(1 5 7) with no component switching or external adjust-
ments
Y No manufacturing trims required internal VCO capaci-
tor trimmed on chip
Y No costly high-precision components needed
Y Low phase jitter (1 3 ns at 100 kHz)
Y DC controlled H phase and duty cycle
Y Video mute pulse for blanking during H frequency
transitions
Y Input sync prioritization
Y Clamp pulse position and width control
Y Continuous clamp pulse output even with no sync input
Y Resistor-programmable minimum and maximum VCO
frequency
Y X-ray input disables H drive and mutes video until VCC
powered down
Y H drive disabled for VCC k 9 5V
Y Horizontal output transistor protected against accidental
turn-on during flyback
Y Capacitor-programmable frequency ramping dfVCO dt
protects H output transistor during scanning mode
changes
Connection Diagram
FIGURE 1
Order Number LM1291N
See NS Package Number N28B
C1995 National Semiconductor Corporation TL H 12323
TL H 12323 – 1
RRD-B30M115 Printed in U S A
1 page  
Block Diagram
FIGURE 3
TL H 12323 – 3
Pin Descriptions
See Figures 4 through 15 for input and output schematics
Pin 1 - CLAMP CNTL This low-impedance current-mode
input pin is internally biased to 2V The direction of current
sets the pulse position (back porch or sync-tip) while the
current magnitude sets the pulse width In a typical applica-
tion a control voltage of 0V–4V is applied to this pin
through a 15 kX resistor A voltage below 2V positions the
pulse on the back porch of the horizontal sync pulse and
decreasing voltage narrows the pulse A voltage above 2V
sets the pulse on the H sync-tip (slightly delayed from the
leading edge) and increasing voltage narrows the pulse At
the boundary of the switchover between the two modes
there is a narrow region of uncertainty resulting in oscilla-
tion which should be no problem in most applications
When there is no H sync in sync-tip mode the clamp pulse
is generated by the VCO at the frequency preset by pin 5
(fMIN) This feature is intended for use in On Screen Display
systems
Pin 2 - CLAMP PULSE Active-low clamp pulse output See
Figure 4 for the output schematic
Pin 3 - VIDEO MUTE This NPN open-collector output pro-
duces an active-low pulse when triggered by a step change
of H sync frequency See Figure 5 for the output schematic
Pin 4 - fMAX A resistor from this pin to ground sets the
upper frequency limit of the VCO fMAX is approximately
1 8 c 109
Hz
(RMAX a 500)
Pin 5 - fMIN A resistor from this pin to ground sets the lower
frequency limit of the VCO fMIN is approximately
7 5 c 103 a 5 6 c 108 Hz
(RMIN a 500)
Pin 6 - VREF CAP This is the decoupling pin for the internal
8 2V reference It should be decoupled to pin 21 (GND) via
a short path with a cap of at least 470 mF
Pin 7 - VCC 12V nominal power supply pin This pin should
be decoupled to pin 21 (GND) via a short path with a cap of
at least 47 mF
Pin 8 - V SYNC IN This pin accepts AC-coupled V sync of
either polarity The pin is internally biased at 5 2V its input
resistance is approximately 50 kX For best noise immunity
a resistor of 2 kX or less should be connected from the
input side of the coupling cap to ground See Figure 6 for
the input schematic
Pin 9 - COMP VIDEO IN The composite video sync stripper
is active only when no signal is present at pin 12 (H HV IN)
The signal to pin 9 must have negative-going sync tips
which are at least 0 14V below black level For best noise
immunity a resistor of 2 kX or less should be connected
from the input side of the coupling cap to ground See Fig-
ure 7 for the input schematic
Pin 10 - H HV CAP A capacitor is connected from this pin
to ground for detecting the polarity and existence of H HV
sync at pin 12
5
5 Page 
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| PDF Descargar | [ Datasheet LM1291N.PDF ] | |
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