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PDF TC7SPN3125TU Data sheet ( Hoja de datos )
| Número de pieza | TC7SPN3125TU | |
| Descripción | Low Voltage/Low Power 1-Bit Dual Supply Bus Buffer | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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TC7SPN3125TU
TOSHIBA Digital Integrated Circuit Silicon Monolithic
TC7SPN3125TU
Low Voltage/Low Power 1-Bit Dual Supply Bus Buffer
The TC7SPN3125 is a dual supply, advanced high-speed
CMOS 1-bit dual supply voltage interface bus buffer fabricated
with silicon gate CMOS technology.
It is also designed with over voltage tolerant inputs and
outputs up to 3.6 V.
Designed for use as an interface between a 1.2-V, 1.5-V, 1.8-V,
or 2.5-V bus and a 1.8-V, 2.5-V or 3.6-V bus in mixed 1.2-V, 1.5-V,
1.8-V or 2.5-V/1.8-V, 2.5-V or 3.6-V supply systems.
The A-input interfaces with the 1.2-V, 1.5-V, 1.8-V or 2.5-V bus,
the B-output with the 1.8-V, 2.5-V, 3.3-V bus.
The enable input (OE) can be used to disable the device so that
Weight: 0.007 g (typ.)
the signal lines are effectively isolated.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
Features (Note)
• Level converter for interfacing 1.2-V to 1.8-V, 1.2-V to 2.5-V, 1.2-V to 3.3-V, 1.5-V to 2.5-V, 1.5-V to 3.3-V, 1.8-V
to 2.5-V, 1.8-V to 3.3-V or 2.5 V to 3.3-V system.
• High-speed operation : tpd = 13.7 ns (max) (VCCA = 2.5 ± 0.2 V, VCCB = 3.3 ± 0.3 V)
tpd = 14.8 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 3.3 ± 0.3 V)
tpd = 16.0 ns (max) (VCCA = 1.5 ± 0.1 V, VCCB = 3.3 ± 0.3 V)
tpd = 29 ns (max) (VCCA = 1.2 ± 0.1 V, VCCB = 3.3 ± 0.3 V)
tpd = 18.5 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 2.5 ± 0.2 V)
tpd = 19.7 ns (max) (VCCA = 1.5 ± 0.15 V, VCCB = 2.5 ± 0.2 V)
tpd = 33 ns (max) (VCCA = 1.2 ± 0.15 V, VCCB = 2.5 ± 0.2 V)
tpd = 43 ns (max) (VCCA = 1.2 ± 0.1 V, VCCB = 1.8 ± 0.15 V)
• Output current : IOH/IOL = ±3 mA (min) (VCC = 3.0 V)
IOH/IOL = ±2mA (min) (VCC = 2.3 V)
IOH/IOL = ±0.5 mA (min) (VCC = 1.65 V)
• Latch-up performance: -300 mA
• ESD performance: Machine model ≥ ±200 V
Human body model ≥ ±2000 V
• Ultra-small package: UF6
• Low current consumption : Using the new circuit significantly reduces current consumption when OE = “H”.
Suitable for battery-driven applications such as PDAs and cellular phones.
• 3.6-V tolerant function and power-down protection provided on all inputs and outputs.
Note: Do not apply a signal to any bus pins when it is in the output mode. Damage may result.
1 2007-10-19
1 page  
AC Characteristics (Ta = −40 to 85°C, Input: tr = tf = 2.0 ns)
wwwV.DCaCtaASh=ee2t4.U5.c±om0.2 V, VCCB = 3.3 ± 0.3 V
Characteristics
Propagation delay time
(A1 → B1)
3-state output enable time
( OE → B1)
3-state output disable time
( OE → B1)
Symbol
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ
Test Condition
Figure 1, Figure 2
Figure 1, Figure 3
Figure 1, Figure 3
VCCA = 1.8 ± 0.15 V, VCCB = 3.3 ± 0.3 V
Characteristics
Propagation delay time
(A1 → B1)
3-state output enable time
( OE → B1)
3-state output disable time
( OE → B1)
Symbol
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ
Test Condition
Figure 1, Figure 2
Figure 1, Figure 3
Figure 1, Figure 3
VCCA = 1.5 ± 0.1 V, VCCB = 3.3 ± 0.3 V
Characteristics
Propagation delay time
(A1 → B1)
3-state output enable time
( OE → B1)
3-state output disable time
( OE → B1)
Symbol
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ
Test Condition
Figure 1, Figure 2
Figure 1, Figure 3
Figure 1, Figure 3
VCCA = 1.2 ± 0.1 V, VCCB = 3.3 ± 0.3 V
Characteristics
Propagation delay time
(A1 → B1)
3-state output enable time
( OE → B1)
3-state output disable time
( OE → B1)
Symbol
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ
Test Condition
Figure 1, Figure 2
Figure 1, Figure 3
Figure 1, Figure 3
TC7SPN3125TU
Min Max Unit
1.0 13.7
1.0 16.6 ns
1.0 7.2
Min Max Unit
1.0 14.8
1.0 18.9 ns
1.0 8.7
Min Max Unit
1.0 16.0
1.0 22.8 ns
1.0 10.2
Min Max Unit
1.0 29
1.0 63
ns
1.0 23
5 2007-10-19
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet TC7SPN3125TU.PDF ] | |
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