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PDF LM1238 Data sheet ( Hoja de datos )

Número de pieza LM1238
Descripción 110 MHz I2C Compatible RGB Preamplifier with Internal Simple OSD Generator and 4 DACs
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! LM1238 Hoja de datos, Descripción, Manual

June 2003
LM1238
110 MHz I2C Compatible RGB Preamplifier with Internal
Simple OSD Generator and 4 DACs
General Description
The LM1238 pre-amp is an integrated, three channel video
pre-amp. It has an I2C compatible interface which allows
control of all the parameters necessary to directly setup and
adjust the gain and contrast in the CRT display. Four I2C
compatible DACs are available to control monitor bias and
brightness circuits. The LM1238 preamp is designed to be
100% compatible with the LM246x high gain driver family
and the LM2479/80 Clamp ICs.
Black level clamping of the video signal is carried out directly
on the AC coupled input signal into the high impedance
pre-amplifier inputs, eliminating the need for additional
clamp capacitors. Horizontal and vertical blanking of the
outputs is provided. Vertical blanking is optional and its
duration is register programmable.
Features
n I2C compatible microcontroller interface
n Internal OSD generator with 16 sets of color icons
n OSD override allows OSD messages to be displayed
while blanking input video
n Internally generated burn-in screen
n 4 DAC outputs (8-bit resolution) for bus controlled CRT
bias and brightness
n Spot killer which blanks the video outputs when VCC
falls below the specified threshold
n Suitable for use with discrete or integrated clamp, with
software configurable brightness mixer
n H and V blanking (V blanking is optional and has
register programmable width)
n Power Saving Mode with 65% power reduction
n Matched to LM246x driver and 2479/80 clamp
Applications
n Low end 15" and 17" bus controlled monitors with OSD
n 1024x768 displays up to 85 Hz requiring OSD capability
n Very low cost systems with LM246x driver
Block and Connection Diagram
FIGURE 1. Order Number LM1238AAC/NA
See NS Package Number N24D
20038701
© 2003 National Semiconductor Corporation DS200387
www.national.com

1 page




LM1238 pdf
System Interface Signal Characteristics (Continued)
Note 5: Input from signal generator: tr, tf < 1 ns.
Note 6: Typical specifications are specified at +25˚C and represent the most likely parametric norm.
Note 7: Tested limits are guaranteed to National’s AOQL; (Average Outgoing Quality Level).
Note 8: The supply current specified is the quiescent current for VCC and 5V Dig with RL = . Load resistors are not required and are not used in the test circuit,
therefore all the supply current is used by the pre-amp.
Note 9: Linearity Error is the maximum variation in step height of a 16 step staircase input signal waveform with a 0.7 VP-P level at the input. All 16 steps equal,
with each at least 100 ns in duration.
Note 10: dt/dVCC = 200*(t5.5V–t4.5V)/ ((t5.5V + t4.5V)) %/V, where:
t5.5V is the rise or fall time at VCC = 5.5V, and t4.5V is the rise or fall time at VCC = 4.5V.
Note 11: AV track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages. It is the difference in
gain change between any two amplifiers with the contrast set to AVC−50% and measured relative to the AV max condition. For example, at AV max the three
amplifiers’ gains might be 12.1 dB, 11.9 dB, and 11.8 dB and change to 2.2 dB, 1.9 dB and 1.7 dB respectively for contrast set to AVC−50%. This yields a typical
gain change of 10.0 dB with a tracking change of ±0.2 dB.
Note 12: ABL should provide smooth decrease in gain over the operational range of 0 dB to −5 dB
AABL = A(VABL = VABL MAX GAIN) – A (VABL = VABL MIN GAIN)
Beyond −5 dB the gain characteristics, linearity and pulse response may depart from normal values.
Note 13: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specific voltage, then discharged directly into the
IC with no external series resistor (resistance of discharge path must be under 50).
Note 14: Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier
inputs to simulate generator loading. Repeat test at fIN = 10 MHz for VSEP 10 MHZ.
Note 15: A minimum pulse width of 200 ns is the guaranteed minimum for a horizontal line of 15 kHz. This limit is guaranteed by design. If a lower line rate is used
then a longer clamp pulse may be required.
Note 16: Adjust input frequency from 10 MHz (AV max reference level) to the −3 dB corner frequency (f−3 dB).
Note 17: Once the spot killer has been activated, the LM1238 remains in the off state until VCC is cycled (reduced below 0.5V and then restored to 5V).
Hexadecimal and Binary Notation
Hexadecimal numbers appear frequently throughout this
document, representing slave and register addresses, and
register values. These appear in the format “0x...”. For ex-
ample, the slave address for writing the registers of the
LM1238 is hexadecimal BA, written as 0xBA. On the other
hand, binary values, where the individual bit values are
shown, are indicated by a trailing “b”. For example, 0xBA is
equal to 10111010b. A subset of bits within a register is
referred to by the bit numbers in brackets following the
register value. For example, the OSD contrast bits are the
fourth and fifth bits of register 0x0818. Since the first bit is bit
0, the OSD contrast register is 0x0818[4:3].
Register Test Settings
Table 1 shows the definitions of the Test Settings 1–8 re-
ferred to in the specifications sections. Each test setting is a
combination of five hexadecimal register values, Contrast,
Gain (Blue, Red, Green) and DC offset.
Control No. of Bits
Contrast
7
B, R, G
Gain
DC Offset
7
3
1
0x7F
(Max)
0x7F
(Max)
0x00
(Min)
TABLE 1. Test Setting Definitions
2
0x00
Min
0x7F
(Max)
0x05
3
0x7F
(Max)
0x7F
(Max)
0x07
(Max)
Test Settings
45
0x7F
0x40
(Max)
(50.4%)
Set VO to
2 VP-P
0x05
0x7F
(Max)
0x05
6
0x7F
(Max)
0x40
(50%)
0x05
7
0x7F
(Max)
0x00
(Min)
0x05
8
0x7F
(Max)
0x7F
(Max)
0x05
5 www.national.com

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LM1238 arduino
Schematic Diagram
FIGURE 9. LM123x-LM246x Demo Board Schematic
20038716
11 www.national.com

11 Page







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