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PDF HD64F2194 Data sheet ( Hoja de datos )
| Número de pieza | HD64F2194 | |
| Descripción | (HD643219x) 16-Bit Single-Chip Microcomputer | |
| Fabricantes | Renesas Technology | |
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REJ09B0328-0300
The revision list can be viewed directly by clicking the title page.
www.DaTtahSehereet4vUi.scoiomn list summarizes the locations of revisions and
additions. Details should always be checked by referring to the
relevant text.
16
H8S/2194 Group, H8S/2194C Group,
H8S/2194F-ZTAT™,
H8S/2194C F-ZTAT™
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2100 Series
H8S/2194
H8S/2193
H8S/2192
H8S/2191
H8S/2194C
H8S/2194B
H8S/2194A
HD6432194
HD64F2194
HD6432193
HD6432192
HD6432191
HD6432194C
HD64F2194C
HD6432194B
HD6432194A
Rev.3.00
Revision Date: Jan. 10, 2007
1 page  
Main Revisions for This Edition
Item
Page
All www.DataSheet4U.co—m
2.8.1 Overview
Figure 2.15 State
Transitions
54
4.2.3 Timer Register 79
A (TMA)
4.6.1 Standby Mode 83
4.6.2 Clearing
Standby Mode
83
6.2.6 Port Mode
Register (PMR1)
7.2.5 Register
Configuration
Table 7.3 Flash
Memory Registers
7.4.1 Boot Mode
106
132
143
8.4.1 Boot Mode
191
8.5
Programming/Erasing
Flash Memory
195
Revision (See Manual for Details)
• Notification of change in company name amended
(Before) Hitachi, Ltd. → (After) Renesas Technology Corp.
• Product naming convention amended
(Before) H8S/2194 Series → (After) H8S/2194 Group
(Before) H8S/2194C Series → (After) H8S/2194C Group
Figure 2.15 amended
RES = High
SLEEP instruction with LSON = 0, TMA3 = 0, SSBY = 0
Table amended
• Timer A counts φ-based prescalar (PSS) divided clock pulses
• Timer A counts φw-based prescalar (PSW) divided clock
pulses
Description amended
… RAM as well as functions of the SCI1, timer X1 …
(1) Clearing with an Interrupt
... in bits STS2 to STS0 in SBYCR, stable clocks are supplied
...
Table amended
P1n/IRQn pin functions as the IRQn input pin
Access size description deleted from table 7.3
(1) Automatic SCI Bit Rate Adjustment
Description amended
… bit rate should be set to (4800, or 9600) bps. …
(1) Automatic SCI Bit Rate Adjustment
Description amended
… bit rate should be set to (4800, or 9600) bps. …
Description amended
… PSU2, ESU2, P2, E2, PV2, and EV2 bits in FLMCR2. …
Rev.3.00 Jan. 10, 2007 page v of xxxvi
REJ09B0328-0300
5 Page 
Item
Page
28.13.6 Operation 751
Figure 28.50 Example
of CTLM Switchover
Timingw(wWwh.DeantaPShhaeseet4U.com
Control Is Performed
by REF30P and
DVCFG2 in REC
Mode)
Figure 28.51 Example 752
of CTLM Switchover
Timing (When Phase
Control Is Performed
by CREF and DVCFG2
in REC Mode)
28.18.9 CTL Output 762
Section
Table 28.21 REC-CTL
Duty Register and CTL
Outputs
28.15.6 Noise
Detection
790
29.2.7 Flash Memory 824
Characteristics
Table 29.12 Flash
Memory Characteristics
(Preliminary)
825
Revision (See Manual for Details)
Figure 28.50 amended
(Before) PDCR3 → (After) PCDR3
Figure 28.51 amended
Ta is the interval calculated from RCDR3. …
Table 28.21 amended
(Before) 65.5 ±0.5% → (After) 62.5 ±0.5%
(1) Example of Setting
Description amended
∴HPWR3 - 0 = H'B
Table 29.12 amended
Item
Symbol Min Typ Max Unit
Erasing time*1*3*5
tE 100 1200 ms/
block
Reprogramming count
NWEC
100 10000 —
*7 *8
Times
Data retention time*9
tDRP
At Wait time after SWE-bit setting*1x
Programming
10 — — Years
10 — — μs
Test
Conditions
Notes 7 to 9 added
Notes: 7. Minimum number of times for which all
characteristics are guaranteed after rewriting (Guarantee range
is 1 to minimum value).
8. Reference value for 25°C (as a guideline, rewriting should
normally function up to this value).
9. Data retention characteristic when rewriting is performed
within the specification range, including the minimum value.
Rev.3.00 Jan. 10, 2007 page xi of xxxvi
REJ09B0328-0300
11 Page | ||
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