PDF ADAU1761 Data sheet ( Hoja de datos )

Número de pieza	ADAU1761
Descripción	24-Bit Audio Codec
Fabricantes	Analog Devices
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No Preview Available ! www.DataSheet4U.com SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL ADAU1761 FEATURES GENERAL DESCRIPTION SigmaDSP 28-/56-bit 50 MIPS digital audio processor Fully programmable with SigmaStudio graphical tool 24-bit stereo audio ADC and DAC: >98 dB SNR Sampling rates from 8 kHz to 96 kHz Low power: 5 mW record, 5 mW playback, 48 kHz at 1.8 V 6 analog input pins, configurable for single-ended or differential inputs Flexible analog input/output mixers Stereo digital microphone input Analog outputs: 2 differential stereo, 2 single-ended stereo, 1 mono headphone driver output PLL supporting input clocks from 8 MHz to 27 MHz Analog automatic level control (ALC) Microphone bias reference voltage Analog and digital I/O: 1.8 V to 3.65 V I2C and SPI control interfaces Digital audio serial data I/O: stereo and time-division multiplexing (TDM) modes Software-controllable clickless mute Software power-down GPIO pins for digital controls and outputs 32-lead, 5 mm × 5 mm LFCSP −40°C to +85°C operating temperature range APPLICATIONS Smartphones/multimedia phones Digital still cameras/digital video cameras Portable media players/portable audio players Phone accessories products The ADAU1761 is a low power, stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record and playback at 10 mW from a 1.8 V analog supply. The stereo audio ADCs and DACs support sample rates from 8 kHz to 96 kHz as well as a digital volume control. The SigmaDSP® core features 28-bit processing (56-bit double precision). The processor allows system designers to compensate for the real-world limitations of microphones, speakers, amplifiers, and listening environments, resulting in a dramatic improvement in the perceived audio quality through equalization, multiband compression, limiting, and third-party branded algorithms. The SigmaStudio™ graphical development tool is used to program the ADAU1761. This software includes audio processing blocks such as filters, dynamics processors, mixers, and low level DSP functions for fast development of custom signal flows. The record path includes an integrated microphone bias circuit and six inputs. The inputs can be mixed and muxed before the ADC, or they can be configured to bypass the ADC. The ADAU1761 includes a stereo digital microphone input. The ADAU1761 includes five high power output drivers (two differential and three single-ended), supporting stereo head- phones, an earpiece, or other output transducer. AC-coupled or capless configurations are supported. Individual fine level controls are supported on all analog outputs. The output mixer stage allows for flexible routing of audio. FUNCTIONAL BLOCK DIAGRAM JACKDET/MICIN HP JACK REGULATOR DETECTION ADAU1761 LAUX LINP LINN RINP RINN RAUX INPUT MIXERS ALC ADC ADC ADC DAC DIGITAL DIGITAL FILTERS FILTERS DAC DAC OUTPUT MIXERS LOUTP LOUTN LHP MONOOUT RHP ROUTP ROUTN MICBIAS MICROPHONE BIAS PLL SERIAL DATA INPUT/OUTPUT PORTS I2C/SPI CONTROL PORT MCLK ADDR0/ ADDR1/ SCL/ SDA/ CLATCH CDATA CCLK COUT Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. 1 page Pwawrawm.DeattearSheet4U.com MICROPHONE BIAS Bias Voltage 0.65 × AVDD 0.90 × AVDD Bias Current Source Noise in the Signal Bandwidth DIGITAL-TO-ANALOG CONVERTERS DAC Resolution Digital Attenuation Step Digital Attenuation Range DAC TO LINE OUTPUT Full-Scale Output Voltage (0 dB) Analog Volume Control Step Analog Volume Control Range Mute Attenuation Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Power Supply Rejection Ratio Gain Error Interchannel Gain Mismatch Offset Error Interchannel Isolation DAC TO CAPLESS HEADPHONE OUTPUT Total Harmonic Distortion + Noise 16 Ω load 32 Ω load Power Supply Rejection Ratio Test Conditions/Comments MBIEN = 1 AVDD = 1.8 V, MBI = 1 AVDD = 3.3 V, MBI = 1 AVDD = 1.8 V, MBI = 0 AVDD = 3.3 V, MBI = 0 AVDD = 3.3 V, MBI = 0, MPERF = 1 AVDD = 3.3 V, 1 kHz to 20 kHz MBI = 0, MPERF = 0 MBI = 0, MPERF = 1 MBI = 1, MPERF = 0 MBI = 1, MPERF = 1 DAC performance excludes mixers and headphone amplifier All DACs Scales linearly with AVDD AVDD = 1.8 V AVDD = 3.3 V Line output volume control Line output volume control 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V −1 dBFS AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V CM capacitor = 20 μF 100 mV p-p @ 217 Hz 100 mV p-p @ 1 kHz 1 kHz, 0 dBFS input signal PO = output power per channel −4 dBFS AVDD = 1.8 V, PO = 6.4 mW AVDD = 3.3 V, PO = 21.1 mW AVDD = 1.8 V, PO = 3.8 mW AVDD = 3.3 V, PO = 10.6 mW CM capacitor = 20 μF 100 mV p-p @ 217 Hz 100 mV p-p @ 1 kHz Rev. 0 \| Page 5 of 92 Min −57 ADAU1761 Typ Max Unit 1.17 2.145 1.62 2.97 42 85 25 37 3 24 0.375 95 AVDD/3.3 0.55 (1.56) 1.0 (2.83) 0.75 1 −87 +6 96 101 93.5 98 −90 −92 96 101 93.5 98 56 70 3 0.005 0 100 V V V V mA nV/√Hz nV/√Hz nV/√Hz nV/√Hz Bits dB dB V rms V rms (V p-p) V rms (V p-p) dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB % dB mV dB −76 dB −82 dB −82 dB −82 dB 56 dB 67 dB 5 Page www.DataSheet4U.tcCoLmS CLATCH CCLK CDATA COUT tCDS tCCPH tCCPL tCDH Figure 4. SPI Port Timing ADAU1761 tCLH tCLPH tCOD SDA SCL tSCH tSCR tDS tSCLH tSCH tSCLL tSCF tSCS Figure 5. I2C Port Timing tDCF tDCR tBFT CLK DATA1/ DATA2 DATA1 tDDV tDDH DATA2 DATA1 tDDH tDDV DATA2 Figure 6. Digital Microphone Timing Rev. 0 \| Page 11 of 92 11 Page

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