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Numéro de référence | IDT70V38L | ||
Description | HIGH-SPEED 3.3V 64K x 18 DUAL-PORT STATIC RAM | ||
Fabricant | Integrated Device Technology | ||
Logo | |||
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HIGH-SPEED 3.3V
64K x 18 DUAL-PORT
STATIC RAM
IDT70V38L
Features
◆ True Dual-Ported memory cells which allow simultaneous
access of the same memory location
◆ High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
◆ Low-power operation
– IDT70V38L
Active: 440mW (typ.)
Standby: 660µW (typ.)
◆ Dual chip enables allow for depth expansion without
external logic
◆ IDT70V38 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
OEL
LBL
◆ M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆ Busy and Interrupt Flags
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
◆ LVTTL-compatible, single 3.3V (±0.3V) power supply
◆ Available in a 100-pin TQFP
◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds
R/WR
UBR
CE0R
CE1R
OER
LBR
I/O 9-17L
I/O 0-8L
BUSYL (1,2)
I/O
Control
I/O
Control
A15L
A0L
Address
Decoder
16
CE0L
CE1L
OEL
R/WL
64Kx18
MEMORY
ARRAY
70V38
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
16
SEML
INT
(2)
L
M/S(1)
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
©2003 Integrated Device Technology, Inc.
1
Address
Decoder
I/O9-17R
I/O0-8R
BUSYR (1,2)
A15R
A0R
.
CE0R
CE1R
OER
R/WR
SEMR
INTR (2)
4850 drw 01
SEPTEMBER 2003
DSC-4850/3
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Pages | Pages 17 | ||
Télécharger | [ IDT70V38L ] |
No | Description détaillée | Fabricant |
IDT70V38L | HIGH-SPEED 3.3V 64K x 18 DUAL-PORT STATIC RAM | Integrated Device Technology |
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