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PDF ADECB1608 Data sheet ( Hoja de datos )
| Número de pieza | ADECB1608 | |
| Descripción | DDR SDRAM 200pin DIMM | |
| Fabricantes | A-Data Technology | |
| Logotipo |  |
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A-Data
Revision History
www.DataSheet4U.com
Revision 1 ( Dec. 2001 )
1.Fister release.
Revision 2 ( Apr. 2002 )
1. Changed module current specification.
2. Add Performance range.
3. Changed AC Characteristics.
4. Changed typo size on module PCB in package dimensions.
ADECB1608
Rev 2 Apr. 2002
1
1 page  
A-Data
ADECB1608
www.DataSheet4U.com
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, Vout
-0.5~3.6
V
Voltage on VDD supply relative to Vss
VDD
-1.0~3.6
V
Voltage on VDDQ supply relative to Vss
VDDQ
-0.5~3.6
V
Storage temperature
TSTG
-55~+150
℃
Power dissipation
PD 8 W
Short circuit current
IOS 50 mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter
Symbol
Min
Max Unit
Note
Supply voltage
VDD, VDDQ
2.3
2.7 V
Reference voltage
VREF
VDDQ/2-50mV VDDQ/2+50mV
V
1
Termination voltage
VTT
VREF-0.04
VREF+0.04
2
Input logic high voltage
VIH
VREF+0.15
VDDQ+0.3
V
3
Input logic low voltage
VIL
-0.3
VREF-0.15
V
3
Output logic high voltage
VOH
VTT+0.84
-
V IOH=-16.8mA
Output logic low voltage
VOL
-
VTT-0.84
V
IOL=16.8mA
Input voltage Level
VIN
-0.3
VDDQ+0.3
V
Input Differential Voltage
VID
0.3
VDDQ+0.6
V
4
Input crossing point voltage
VIX
1.15
1.35 V
5
Input leakage current
IIL -2
2 uA
Output leakage current
IOL
-5
5 uA
Note : 1. Includes±25mV margin for DC offset on VREF, and a combined total of ±50mV margin for all AC noise and
DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF
and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be
de-coupled with an inductance of ≤ 3nH.
2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected
to be set equal to VREF, and must track variations in the DC level of VREF
3.These parameters should be tested at the pin on actual components and may be checked at either the pin or
the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been
bandwidth limited to 200MHz.
4.VID is the magnitude of the difference between the input level on CK and the input level on /CK.
5.The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC
level of the same.
Rev 2 Apr. 2002
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet ADECB1608.PDF ] | |
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