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PDF IDT72V3633 Data sheet ( Hoja de datos )
| Número de pieza | IDT72V3633 | |
| Descripción | (IDT72V36x3) 3.3 VOLT CMOS SyncFIFO | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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3.3 VOLT CMOS SyncFIFOTM
WITH BUS-MATCHING
256 x 36, 512 x 36,
1,024 x 36
IDT72V3623
IDT72V3633
IDT72V3643
.EATURES:
• Memory storage capacity:
IDT72V3623–256 x 36
IDT72V3633–512 x 36
IDT72V3643–1,024 x 36
• Clock frequencies up to 100 MHz (6.5 ns access time)
• Clocked FIFO buffering data from Port A to Port B
• IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
• Serial or parallel programming of partial flags
• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
• Big- or Little-Endian format for word and byte bus sizes
• Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
• Easily expandable in width and depth
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
• Pin and functionally compatible versions of the 5V operating
IDT723623/723633/723643
• Industrial temperature range (–40°C to +85°C) is available
.UNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
RS1
RS2
PRS
Port-A
Control
Logic
FIFO1
Mail1,
Mail2,
Reset
Logic
36
Mail 1
Register
36
RAM ARRAY
256 x 36
36
512 x 36
1,024 x 36
MBF1
36
A0-A35
Write
Pointer
Read
Pointer
B0-B35
FF/IR
AF
Status Flag
Logic
EF/OR
AE
SPM
FS0/SD
FS1/SEN
MBF2
36
Programmable Flag
Timing
Offset Registers
Mode
10
Mail 2
Register
36
Port-B
Control
Logic
FWFT
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
4662 drw01
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications sunject to change without notice.
AUGUST 2001
DSC-4662/3
1 page  
IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURERANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol Name
MBwAww.DataShPeoertt4AU.Mcoamilbox
Select
I/O Description
I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
MBB
MBF1
MBF2
Port B Mailbox
Select
Mail1 Register Flag
Mail2 Register Flag
I A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output and
a LOW level selects FIFO data for output.
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-
HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH
following either a Reset (RS1) or Partial Reset (PRS).
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-
HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH
following either a Reset (RS2) or Partial Reset (PRS).
RS1, RS2 Resets
PRS PartialReset
I A LOW on both pins initializes the FIFO read and write pointers to the first location of memory and
setsthePortBoutputregistertoallzeroes. ALOW-to-HIGHtransitionon RS1 selects the programming
method (serial or parallel) and one of three programmable flag default offsets. It also configures Port
B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while RS1 is LOW.
I A LOW on this pin initializes the FIFO read and write pointers to the first location of memory and sets
the Port B output register to all zeroes. During Partial Reset, thecurrentlyselectedbussize,endian
arrangement, programming method (serial or parallel), and programmable flag settings are all retained.
SIZE
SPM
W/RA
W/RB
Bus Size Select
(Port B)
Serial Programming
Mode
Port A Write/
Read Select
Port B Write/
Read Select
I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin
when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size
and endian arrangement for Port B. The level of SIZE must be static throughout device operation.
I ALOWonthispinselectsserialprogrammingofpartialflagoffsets. AHIGHonthispinselectsparallel
programming or default offsets (8, 16, or 64).
I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
I A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
5
5 Page 
IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING
256 x 36, 512 x 36, 1,024 x 36
TABLE 1 .LAG PROGRAMMING
SPM
FS1/SEN
FS0/SD
RS1
wwHw.DataSheet4U.coHm
H
↑
HH L ↑
HL H ↑
HL L ↑
LH L ↑
LH H ↑
LL H ↑
LL
L
NOTE:
1. X register holds the offset for AE; Y register holds the offset for AF.
↑
COMMERCIAL TEMPERATURERANGE
X AND Y REGlSTERS(1)
64
16
8
Parallel programming via Port A
Serial Programming via SD
reserved
reserved
reserved
thethirdwritecycletheFIFOisreadytobeloadedwithadataword. SeeFigure
5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values after Reset (IDT Standard and FWFT modes), for a detailed
timing diagram. The Port A data inputs used by the offset registers are (A7-A0),
(A8-A0), or (A9-A0) for the IDT72V3623, IDT72V3633 or IDT72V3643,
respectively. Thehighestnumberedinputisusedasthemostsignificantbitof
the binary number in each case. Valid programming values for the registers
range from 1 to 252 for the IDT72V3623; 1 to 508 for the IDT72V3633; and
1 to 1,020 for the IDT72V3643. After all the offset registers are programmed
from Port A, the FIFO begins normal operation.
— SERIAL LOAD
To program the X and Y registers serially, initiate a Reset with SPM LOW,
FS0/SDLOWandFS1/SEN HIGHduringtheLOW-to-HIGHtransitionofRS1.
After this reset is complete, the X and Y register values are loaded bit-wise
through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the
FS1/SEN inputisLOW.Thereare16-,18-or20-bitwritesneededtocomplete
the programming for the IDT72V3623, IDT72V3633 or the IDT72V3643,
respectively. ThetworegistersarewrittenintheorderY,X. Eachregistervalue
can be programmed from 1 to 252 (IDT72V3623), 1 to 508 (IDT72V3633) or
1 to 1,020 (IDT72V3643).
When the option to program the offset registers serially is chosen, the Full/
Input Ready (FF/IR) flag remains LOW until all register bits are written. FF/IR
is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded
to allow normal FIFO operation.
See Figure 6, Serial Programming of the Almost-Full Flag and Almost-
Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).
FIFO WRITE/READ OPERATION
The state of the Port A data (A0-A35) lines is controlled by Port A Chip
Select (CSA) and Port A Write/Read select (W/RA). The A0-A35 lines are in
the High-impedance state when either CSA or W/RA is HIGH. The A0-A35
lines are active outputs when both CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW,andFF/IRisHIGH(seeTable2). FIFOwritesonPortAareindependent
of any concurrent reads on Port B.
The Port B control signals are identical to those of Port A with the exception
that the Port B Write/Read select (W/RB) is the inverse of the Port A Write/Read
select (W/RA). The state of the Port B data (B0-B35) lines is controlled by the
Port B Chip Select (CSB) and Port B Write/Read select (W/RB). The B0-B35
lines are in the high-impedance state when either CSB is HIGH or W/RB is LOW.
The B0-B35 lines are active outputs when CSB is LOW and W/RB is HIGH.
Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH
transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is
LOW,andEF/ORisHIGH(seeTable3). FIFOreadsonPortBareindependent
of any concurrent writes on Port A.
The setup and hold time constraints to the port clocks for the port Chip
Selects and Write/Read selects are only for enabling write and read operations
andarenotrelatedtohigh-impedancecontrolofthedataoutputs. Ifaportenable
is LOW during a clock cycle, the port’s Chip Select and Write/Read select may
change states during the setup and hold time window of the cycle.
When operating the FIFO in FWFT mode and the Output Ready flag is
LOW, the next word written is automatically sent to the FIFO’s output register by
the LOW-to-HIGH transition of the port clock that sets the Output Ready flag
HIGH. WhentheOutputReadyflagisHIGH,dataresidingintheFIFO’smemory
array is clocked to the output register only when a read is selected using the
port’s Chip Select, Write/Read select, Enable, and Mailbox select.
When operating the FIFO in IDT Standard mode, regardless of whether
the Empty Flag is LOW or HIGH, data residing in the FIFO’s memory array is
clocked to the output register only when a read is selected using the port’s Chip
Select, Write/Read select, Enable, and Mailbox select. Port A Write timing
diagram can be found in Figure 7. Relevant Port B Read timing diagrams
together with Bus-Matching and Endian select can be found in Figure 8, 9 and
10.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at least two flip-flop
stages. Thisisdonetoimproveflag-signalreliabilitybyreducingtheprobability
of metastable events when CLKA and CLKB operate asynchronously to one
another. FF/IR, and AF are synchronized to CLKA. EF/OR and AE are
synchronized to CLKB. Table 4 shows the relationship of each port flag to the
number of words stored in memory.
EMPTY/OUTPUT READY FLAGS (EF/OR)
Thesearedualpurposeflags. IntheFWFTmode,theOutputReady(OR)
functionisselected. WhentheOutput-ReadyflagisHIGH,newdataispresent
in the FIFO output register. When the Output Ready flag is LOW, the previous
data word is present in the FIFO output register and attempted FIFO reads are
ignored.
IntheIDTStandardmode,theEmptyFlag(EF)functionisselected. When
the Empty Flag is HIGH, data is available in the FIFO’s memory for reading to
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet IDT72V3633.PDF ] | |
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