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PDF IDT72V3624 Data sheet ( Hoja de datos )
| Número de pieza | IDT72V3624 | |
| Descripción | (IDT72V36x4) 3.3 VOLT CMOS SyncBiFIFO | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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3.3 VOLT CMOS SyncBiFIFOTM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
IDT72V3624
IDT72V3634
IDT72V3644
.EATURES:
• Memory storage capacity:
IDT72V3624–256 x 36 x 2
IDT72V3634–512 x 36 x 2
IDT72V3644–1,024 x 36 x 2
• Clock frequencies up to 100 MHz (6.5ns access time)
• Two independent clocked FIFOs buffering data in opposite
directions
• Select IDT Standard timing (using EFA, EFB, FFA, and FFB
flags functions) or First Word Fall Through Timing (using ORA,
ORB, IRA, and IRB flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
• Serial or parallel programming of partial flags
• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
• Big- or Little-Endian format for word and byte bus sizes
• Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or coinci-
dent (simultaneous reading and writing of data on a single clock
edge is permitted)
• Auto power down minimizes power dissipation
• Available in space saving 128-pin Thin Quad Flatpack (TQFP)
• Pin and functionally compatible version of the 5V operating
IDT723624/723634/723644
• Industrial temperature range (–40°C to +85°C) is available
.UNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A0-A35
EFA/ORA
AEA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
36
36
MBF2
Mail 1
Register
36
RAM ARRAY
256 x 36
36
512 x 36
1,024 x 36
FIFO1
Write
Pointer
Read
Pointer
Status Flag
Logic
Programmable Flag
Offset Registers
Timing
Mode
10
FIFO2
Status Flag
Logic
Read
Pointer
Write
Pointer
RAM ARRAY
36 256 x 36
512 x 36
1,024 x 36
36
Mail 2
Register
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MBF1
36
EFB/ORB
AEB
36
FIFO2,
Mail2
Reset
Logic
Port-B
Control
Logic
FWFT
B0-B35
FFB/IRB
AFB
MRS2
PRS2
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
4664 drw01
AUGUST 2001
DSC-4664/3
1 page  
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
I/O
FSw1/wSwEN.DaFtalaSghOefefst4eUt S.ceolemct 1/ I
Serial Enable,
FS0/SD Flag Offset Select 0/ I
Serial Data
MBA Port A Mailbox
Select
MBB Port B Mailbox
Select
MBF1 Mail1Register
Flag
I
I
O
MBF2 Mail2Register
Flag
O
MRS1 FIFO1 Master
Reset
I
MRS2 FIFO2 Master
Reset
I
PRS1 FIFO1 Partial
Reset
PRS2 FIFO2 Partial
Reset
SIZE Bus Size Select
I
I
I
SPM
W/RA
W/RB
Serial Programming
Mode
Port-A Write/
Read Select
Port-B Write/
Read Select
I
I
I
Description
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master
Reset, FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three offset
register programming methods are available: automatically load one of three preset values (8, 16, or 64),
parallel load from Port A, and serial load.
When serial load is selected for flag offset register programming, FS1/SEN is used as an enable synchronous
to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present
on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 32
for the 72V3624, 36 for the 72V3634, and 40 for the 72V3644. The first bit write stores the Y-register (Y1)
MSB and the last bit write stores the X-register (X2) LSB.
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level
selects FIFO2 output register data for output.
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35
outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level
selects FIFO1 output register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to
the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB
when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial
Reset of FIFO1.
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the
mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA
when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial
Reset of FIFO2.
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the
Port B output register to all zeroes. A LOW-to-HIGH transition onMRS1selectstheprogrammingmethod(serial
or parallel) and one of three programmable flag default offsets for FIFO1 and FIFO2. It also configures Port
Bforbussizeandendianarrangement. FourLOW-to-HIGHtransitionsofCLKA andfourLOW-to-HIGHtransitions
of CLKB must occur while MRS1 is LOW.
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the
PortAoutputregistertoallzeroes. ALOW-to-HIGHtransitiononMRS2,toggledsimultaneouslywithMRS1,selects
theprogrammingmethod(serialorparallel)andoneoftheprogrammableflagdefaultoffsetsforFIFO2. FourLOW-
to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is LOW.
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the
Port B output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement,
programming method (serial or parallel), and programmable flag settings are all retained.
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port
A output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement,
programming method (serial or parallel), and programmable flag settings are all retained.
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH
selects word (18-bit) bus size. SIZE works with BM andBEtoselectthebussizeandendianarrangementforPort
B. The level of SIZE must be static throughout device operation.
ALOWonthispinselectsserialprogrammingofpartialflagoffsets. AHIGHonthispinselectsparallelprogramming
or default offsets (8, 16, or 64).
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of
CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition of
CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
5
5 Page 
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
labeled Y2. The index of each register name corresponds to its FIFO number.
The offset registers can be loaded with preset values during the reset of a FIFO,
progwrawmwm.DeadtianSphaeraeltl4eUl u.csoinmg the FIFO’s Port A data inputs, or programmed
in serial using the Serial Data (SD) input (see Table 1).
SPM, FS0/SD, and FS1/SEN function the same way in both IDT Standard
and FWFT modes.
— PRESET VALUES
To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers with
one of the three preset values listed in Table 1, the Serial Program Mode (SPM)
and at least one of the flag-select inputs must be HIGH during the LOW-to-HIGH
transition of its Master Reset input (MRS1, MRS2). For example, to load the
preset value of 64 into X1 and Y1, SPM, FS0 and FS1 must be HIGH when
FlFO1 reset (MRS1) returns HIGH. Flag-offset registers associated with FIFO2
are loaded with one of the preset values in the same way with FIFO2 Master
Reset (MRS2), toggled simultaneously with FIFO1 Master Reset (MRS1). For
relevant preset value loading timing diagram, see Figure 3.
— PARALLEL LOAD FROM PORT A
To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master
Reset on both FlFOs simultaneously withSPM HIGH and FS0 and FS1 LOW
during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is
complete, the first four writes to FIFO1 do not store data in the RAM but load
the offset registers in the order Y1, X1, Y2, X2. The Port A data inputs used by
the offset registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT72V3624,
IDT72V3634, or IDT72V3644, respectively. The highest numbered input is
used as the most significant bit of the binary number in each case. Valid
programming values for the registers range from 1 to 252 for the IDT72V3624;
1 to 508 for the IDT72V3634; and 1 to 1,020 for the IDT72V3644. After all the
offset registers are programmed from Port A, the Port B Full/Input Ready flag
(FFB/IRB) is set HIGH, and both FIFOs begin normal operation. Refer to Figure
5 for a timing diagram illustration of parallel programming of the flag offset values.
— SERIAL LOAD
To program the X1, X2, Y1, and Y2 registers serially, initiate a Master Reset
withSPM LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH
transition of MRS1 and MRS2. After this reset is complete, the X and Y register
values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH
transition of CLKA that the FS1/SEN input is LOW. There are 32-, 36-, or 40-
bit writes needed to complete the programming for the IDT72V3624,
IDT72V3634, or IDT72V3644, respectively. The four registers are written in
theorderY1,X1,Y2,andfinally,X2. Thefirst-bitwritestoresthemostsignificant
bit of the Y1 register and the last-bit write stores the least significant bit of the X2
register. Each register value can be programmed from 1 to 252 (IDT72V3624),
1 to 508 (IDT72V3634), or 1 to 1,020 (IDT72V3644).
When the option to program the offset registers serially is chosen, the Port
A Full/Input Ready (FFA/IRA) flag remains LOW until all register bits are written.
FFA/IRA is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit
is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (FFB/
IRB) flag also remains LOW throughout the serial programming process, until
all register bits are written. FFB/IRB is set HIGH by the LOW-to-HIGH transition
of CLKB after the last bit is loaded to allow normal FIFO2 operation. See Figure
6 for Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (IDT Standard and FWFT Modes) timing diagram.
FIFO WRITE/READ OPERATION
The state of the Port A data (A0-A35) lines is controlled by Port A Chip Select
(CSA) and Port A Write/Read select (W/RA). The A0-A35 lines are in the High-
impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are
active outputs when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA
is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads and
writes on Port A are independent of any concurrent Port B operation.
The Port B control signals are identical to those of Port A with the exception
that the Port B Write/Read select (W/RB) is the inverse of the Port A Write/Read
select (W/RA). The state of the Port B data (B0-B35) lines is controlled by the
Port B Chip Select (CSB) and Port B Write/Read select (W/RB). The B0-B35
lines are in the high-impedance state when either CSB is HIGH or W/RB is
TABLE 1 .LAG PROGRAMMING
SPM FS1/SEN FS0/SD MRS1 MRS2
H HH
↑X
H HH
↑↑
H HL
↑X
H HL
↑↑
H LH ↑X
H LH ↑↑
H LL
↑↑
L HL
↑↑
L HH ↑↑
L LH ↑↑
L L L ↑↑
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
X1 AND Y1 REGlSTERS(1)
64
64
16
16
8
8
Parallel programming via Port A
Serial programming via SD
Reserved
Reserved
Reserved
11
X2 AND Y2 REGlSTERS(2)
X
64
X
16
X
8
Parallel programming via Port A
Serial programming via SD
Reserved
Reserved
Reserved
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT72V3624.PDF ] | |
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