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ICS680-01 fiches techniques PDF

Integrated Circuit Systems - Networking Clock Synthesizer and Zero Delay Buffer

Numéro de référence ICS680-01
Description Networking Clock Synthesizer and Zero Delay Buffer
Fabricant Integrated Circuit Systems 
Logo Integrated Circuit Systems 





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ICS680-01 fiche technique
ICS680-01
Networking Clock Synthesizer and Zero Delay Buffer
www.DataSheet4U.com
Description
Features
The ICS680-01 generates four high-frequency clock
outputs and a reference from a 25 MHz crystal or clock
input. The device includes a low-skew, single input to
four output zero delay clock buffer. It can replace
multiple crystals and oscillators, saving board space
and cost.
The device has a power-down tri-state (PDTS) pin that
place the clock outputs in a high-impedance state when
pulled low. The PDTS pin includes an internal pull-up
resistor.
Block Diagram
Packaged in 24-pin TSSOP
Available in Pb (lead) free package
Replaces multiple crystals and oscillators
Input crystal or clock frequency of 25 MHz
Five output driver driven by external clock
Duty cycle of 45/55
Operating voltage of 3.3 V
Advanced, low-power CMOS process
Fixed output frequencies of 25 MHz and 48 MHz
Selectable output frequencies of 24 MHz, 48 MHz,
50 MHz and 66.6666 MHz
Qx outputs replace costly discrete buffer
Low-skew buffer outputs (250 ps)
VDD
5
S0
S1
25 MHz
Crystal or Clock
X1/ICLK
X2
PLLA
PLLB
PLLC
Crystal
Oscillator
Divide
Logic
and
Output
Enable
Control
CLK1
CLK2
48M
25M
External capacitors
may be required.
QFB
Q0
ICLK
PLL/Buffer
2
GND
PDTS
Q1
Q2
Q3
MDS 680-01 F
1
Revision 020305
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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