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PDF ADC12EU050 Data sheet ( Hoja de datos )
| Número de pieza | ADC12EU050 | |
| Descripción | 40-50 MSPS Analog-to-Digital Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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ADVANCE INFORMATION
January 25, 2008
www.DataSheet4U.com
ADC12EU050
Ultra-Low Power, Octal, 12-bit, 40-50 MSPS Analog-to-
Digital Converter
General Description
NOTE: This is Advance Information for a product cur-
rently in development. ALL specifications are design tar-
gets and are subject to change.
The ADC12EU050 is a 12-bit, ultra-low power, octal A/D con-
verter for use in high performance analog to digital applica-
tions. The ADC12EU050 uses an innovative continuous time
sigma delta architecture offering ultra low power consumption
and an alias free sample bandwidth up to 25MHz. The input
stage of each channel features a proprietary system to ensure
instantaneous recovery from overdrive. Instant overload re-
covery (IOR) with no memory effect guarantees the elimina-
tion of phase errors resulting from out of range input signals.
The ADC12EU050 reduces interconnection complexity by us-
ing programmable serialized outputs which offer the industry
standard LVDS and SLVS modes. Power consumption of only
44mW per channel(@ 50MSPS) gives a total chip power con-
sumption of 350mW. The ADC12EU050 can operate entirely
from a 1.2V supply, although a separate output driver supply
of up to 1.8V can be used. The device operates from -40 to
+85 °C and is supplied in a 10 x 10 mm2, 68 pin package.
Features
■ CT∑ΔADC architecture with 40-50MSPS throughput
■ Anti-alias filter free Nyquist sample range
■ Unique Instant Overload Recovery (IOR)
■ Wide 2.10 VPP input range
■ 1.2V supply voltage
■ Integrated precision LC PLL
■ Serial control via SPI compatible interface
Key Specifications
■ Resolution
12 Bits
■ Conversion Rate
40 to 50 MSPS
■ SNR
■ THD
■ Power Consumption
70 dBFS (typ) @ (fIN = 3.5MHz)
–70 dB (typ) @ (fIN = 3.5MHz)
44 mW/ch (typ) @ 50MSPS
■ 40 mW/ch (typ) @ 40MSPS
■ Total Active Power
350 mW (typ) @ 50MSPS
Consumption
(Equalizer off)
■ Inter-Channel Isolation
■ Operating Temp. Range
>110 dB @ (fIN = 3.5MHz)
-40 to +85 °C
Applications
■ Battery powered portable systems
■ Medical imaging, ultrasound
■ Industrial ultrasound, such as non-destructive testing
■ Communications
© 2008 National Semiconductor Corporation 300511
www.national.com
1 page  
Pin No.
Name
15 DO0+
16 DO0-
18www.DataSheDeOt41U+.com
19 DO1-
20 DO2+
21 DO2-
23 DO3+
24 DO3-
25 DO4+
26 DO4-
28 DO5+
29 DO5-
31 DO6+
32 DO6-
33 DO7+
34 DO7-
36 BCLK+
37 BCLK-
38 WCLK+
39 WCLK-
44 SDATA
45 SCLK
46 SSEL
47 CLK+ (SE)
48 CLK-
POWER SUPPLY
1, 8, 51, 54,
57, 60, 63, 66
0
VA
AGND
11, 12, 42, 43
13, 14, 22,
30, 40, 41
VD
DGND
17, 27, 35
VDR
Type
Function and Connection
Output
Differential Serial Outputs for channels 0 to 7. Each pair of outputs
provides the serial output for the specific channel. The default
output is LVDS format, but programming the appropriate control
registers, the output format can be changed to SLVS.
By programming TX_term (bit 4) in the LVDS Control register, it is
possible to internally terminate these outputs with 100 ohm
resistors.
Output
Output
Input/Output
Input
Input
Input
Power
Ground
Power
Ground
Power
Bit clock. Differential output clock to be used for sampling the serial
outputs. Information on timing can be seen in the Electrical
Specifications section of the datasheet.
By programming TX_term (bit 4) in the LVDS Control register, it is
possible to internally terminate these outputs with 100 ohm
resistors.
Word Clock. Differential output frame clock. Information on timing
can be seen in the Electrical Specifications section of the
datasheet.
By programming TX_term (bit 4) in the LVDS Control register, it is
possible to internally terminate these outputs with 100 ohm
resistors.
SPI data input and output. This pin is used to send and receive SPI
address and data information. The direction of the pin is controlled
internally by the ADC based on the SPI protocol.
SPI clock. In order to use the SPI interface, a clock must be
provided on this pin. The maximum frequency of operation for the
serial interface is 1MHz.
SPI chip select. This active low pin is used to enable the serial
interface.
Differential Input Clock. The input clock must lie in the range of
40MHz to 50MHz. It is used by the PLL to generate the internal
sampling clocks. A single ended clock can also be used, and
should be connected to pin 47.
Analog Power Supply. All pins should be connected to the same
1.2V supply, with voltage limits as in the Electrical Specification.
Analog Ground Return.
Digital Power Supply. Connect to 1.2V, with voltage limits as in the
Electrical Specification.
Digital and Output Driver Ground Return.
Output Driver Power Supply. Can be connected to 1.2V – 1.8V,
depending on application requirements. Voltage limits are
described in more detail in the Electrical Specification.
5 www.national.com
5 Page | ||
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| PDF Descargar | [ Datasheet ADC12EU050.PDF ] | |
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