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PDF TC55V16256JI-15 Data sheet ( Hoja de datos )
| Número de pieza | TC55V16256JI-15 | |
| Descripción | MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS | |
| Fabricantes | Toshiba Semiconductor | |
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TC55V16256JI/FTI-12,-15
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2ww6w2.D,1a4ta4Sh-eWet4OUR.coDm BY 16-BIT CMOS STATIC RAM
DESCRIPTION
The TC55V16256JI/FTI is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 262,144
words by 16 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it
operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode,
and output enable ( OE ) provides fast memory access. Data byte control signals ( LB , UB ) provide lower and upper
byte access. This device is well suited to cache memory applications where high-speed access and high-speed
storage are required. All inputs and outputs are directly LVTTL compatible. The TC55V16256JI/FTI is available in
plastic 44-pin SOJ and 44-pin TSOP with 400mil width for high density surface assembly. The TC55V16256JI/FTI
guarantees −40° to 85°C operating temperature so it is suitable for use in wide operating temperature system.
FEATURES
• Fast access time (the following are maximum values)
TC55V16256JI/FTI-12:12 ns
TC55V16256JI/FTI-15:15 ns
• Low-power dissipation
(the following are maximum values)
Cycle Time 12 15 20 25 ns
Operation (max) 230 200 170 150 mA
Standby:10 mA (both devices)
• Single power supply voltage of 3.3 V ± 0.3 V
• Fully static operation
• All inputs and outputs are LVTTL compatible
• Output buffer control using OE
• Data byte control using LB (I/O1 to I/O8) and
UB (I/O9 to I/O16)
• Package:
SOJ44-P-400-1.27 (JI)
(Weight: 1.64 g typ)
TSOP II44-P-400-0.80 (FTI) (Weight: 0.45 g typ)
PIN ASSIGNMENT (TOP VIEW)
44 PIN SOJ
44 PIN TSOP
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VDD
GND
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A5
A4
43 A6
A3
42 A7
A2
41 OE
A1
40 UB
A0
39 LB
CE
38 I/O16 I/O1
37 I/O15 I/O2
36 I/O14 I/O3
35 I/O13 I/O4
34 GND VDD
33 VDD GND
32 I/O12 I/O5
31 I/O11 I/O6
30 I/O10 I/O7
29 I/O9 I/O8
28 NU
WE
27 A8
A15
26 A9
A14
25 A10 A13
24 A11 A12
23 A17 A16
(TC55V16256JI)
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 34
12 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
(TC55V16256FTI)
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
VDD
I/O12
I/O11
I/O10
I/O9
NU
A8
A9
A10
A11
A17
PIN NAMES
A0 to A17 Address Inputs
I/O1 to I/O16 Data Inputs/Outputs
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
LB , UB Data Byte Control Inputs
VDD
GND
Power (+3.3 V)
Ground
NU Not Usable (Input)
2002-01-07 1/11
1 page  
TC55V16256JI/FTI-12,-15
AC CHARACTERISTICS (Ta = −40° to 85°C (See Note 1), VDD = 3.3 V ± 0.3 V)
wwwR.DEaAtaDSheCeYt4UC.cLoEm
SYMBOL
PARAMETER
tRC
tACC
tCO
tOE
tBA
tOH
tCOE
tOEE
tBE
tCOD
tODO
tBD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Upper Byte, Lower Byte Access Time
Output Data Hold Time from Address Change
Output Enable Time from Chip Enable
Output Enable Time from Output Enable
Output Enable Time from Upper Byte, Lower Byte
Output Disable Time from Chip Enable
Output Disable Time from Output Enable
Output Disable Time from Upper Byte, Lower Byte
TC55V16256JI/FTI
-12 -15
MIN MAX MIN MAX
12 15
12 15
12 15
68
68
34
34
11
11
78
78
78
UNIT
ns
WRITE CYCLE
SYMBOL
PARAMETER
tWC
tWP
tCW
tBW
tAW
tAS
tWR
tDS
tDH
tOEW
tODW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Upper Byte, Lower Byte Enable to End of Write
Address Valid to End of Write
Address Setup Time
Write Recovery Time
Data Setup Time
Data Hold Time
Output Enable Time from Write Enable
Output Disable Time from Write Enable
TC55V16256JI/FTI
-12 -15
MIN MAX MIN MAX
12 15
89
10 12
10 12
10 12
00
00
78
00
11
78
UNIT
ns
AC TEST CONDITIONS
PARAMETER
Input Pulse Level
Input Pulse Rise and Fall Time
Input Timing Measurement
Reference Level
Output Timing Measurement
Reference Level
Output Load
TEST CONDITION
3.0 V/ 0.0 V
2 ns
1.5 V
1.5 V
Fig.1
Fig.1
I/O pin Z0 = 50 Ω
3.3 V
I/O pin
1200 Ω
CL = 30 pF
RL = 50 Ω
CL = 5 pF
870 Ω
VL = 1.5 V
(For tCOE, tOEE, tBE, tCOD,
tBD, tODO, tOEW and tODW)
2002-01-07 5/11
5 Page 
www.DataSheet4U.com
TC55V16256JI/FTI-12,-15
RESTRICTIONS ON PRODUCT USE
000707EBA
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
2002-01-07 11/11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet TC55V16256JI-15.PDF ] | |
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